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Author SHA1 Message Date
Kenneth Graunke 140f53e646 Revert "nir: replace lower_ffma and fuse_ffma with has_ffma" 
This reverts commit 939ddf3f67.

Intel has a separate pass for fusing FFMAs selectively.  We split
these flags in commit 1b72c31e1f and
the reasoning still stands.  The patch being reverted was just a
cleanup, so there should be no issue with reverting it.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6849>
 2020-09-24 13:11:50 -07:00
Marek Olšák 939ddf3f67 nir: replace lower_ffma and fuse_ffma with has_ffma 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
 2020-09-24 12:29:11 +00:00
Marek Olšák f1284505f0 radeonsi: fuse or lower ffma optimally on all chips 
LLVM is going to support the legacy instructions soon.

This change switches FMA to MAD for gfx10.

54793 shaders in 33659 tests
Totals:
SGPRS: 2632554 -> 2629570 (-0.11 %)
VGPRS: 1536364 -> 1535312 (-0.07 %)
Spilled SGPRs: 3602 -> 3562 (-1.11 %)
Spilled VGPRs: 44 -> 40 (-9.09 %)
Private memory VGPRs: 256 -> 256 (0.00 %)
Scratch size: 312 -> 308 (-1.28 %) dwords per thread
Code Size: 55422660 -> 55345408 (-0.14 %) bytes
Max Waves: 963983 -> 964200 (0.02 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
 2020-09-24 12:29:11 +00:00
Marek Olšák 771aad3027 nir: split lower_ffma into lower_ffma16/32/64 
AMD wants different behavior for each bit size

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
 2020-09-24 12:29:11 +00:00
Marek Olšák 21174dedec nir: split fuse_ffma into fuse_ffma16/32/64 
AMD wants different behavior for each bit size

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
 2020-09-24 12:29:11 +00:00
Marek Olšák d3c63d6f60 radeonsi: set flags for FP16 in shaders 
v2: remove the enablement code

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6622>
 2020-09-22 02:44:53 +00:00
Pierre-Eric Pelloux-Prayer f007115e3b radeonsi: change vendor name to AMD 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6754>
 2020-09-21 14:15:03 +02:00
Pierre-Eric Pelloux-Prayer b73e165a04 radeonsi: reduce PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE value 
The new value (64 MB) is a compromise:
- the old value was very large (max_alloc & 0xffffffff) and caused https://gitlab.freedesktop.org/mesa/mesa/-/issues/3301
- amdgpu-pro allows 512MB, nvidia 64MB

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6754>
 2020-09-21 14:15:03 +02:00
Pierre-Eric Pelloux-Prayer 1826367333 radeonsi: move GL vendor workaround to drirc 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6754>
 2020-09-21 14:14:57 +02:00
Pierre-Eric Pelloux-Prayer fc6df020e3 gallium: add PIPE_CAP_MAX_TEXTURE_MB 
Allows driver to override the default value (1024) from mesa.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6754>
 2020-09-21 14:14:48 +02:00
Gert Wollny b155b6869c radeonsi: set compiler flag lower_uniforms_to_ubo 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6316>
 2020-09-16 10:07:42 +00:00
Marek Olšák 758ab39d25 radeonsi: clean up ffma handling 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6596>
 2020-09-16 02:39:02 +00:00
Marek Olšák a407123789 radeonsi: move nir_shader_compiler_options into si_screen 
so that they can be different depending on the GPU (for 16-bit support)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6284>
 2020-09-06 14:36:20 +00:00
Marek Olšák 08ee72100f radeonsi: don't lower indirect IO in GLSL 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6445>
 2020-09-02 22:45:38 -04:00
Pierre-Eric Pelloux-Prayer f8c0e20152 radeonsi: enable PIPE_CAP_NO_CLIP_ON_COPY_TEX 
This fixes specviewperf13 catia test rendering.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6259>
 2020-09-02 11:53:16 +02:00
Rob Clark c4e0cae90c gallium: replace 16BIT_TEMPS cap with 16BIT_CONSTS 
All drivers that support mediump lowering should support 16BIT_TEMPS,
but some do not also want 16b consts to be lowered.  Replace the pipe
cap in preperation to remove LowerPrecisionTemporaries.

Note: also updates reference checksums for the arm64_a630_traces job,
due to lowering more to 16b

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6189>
 2020-08-05 21:00:44 +00:00
Thong Thai 045711dc1c radeonsi: use PIPE_FORMAT_P010 for 10-bit VP9 decoding 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leoliu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5848>
 2020-07-16 17:52:20 +00:00
Marek Olšák 75b59bb1d6 gallium: add PIPE_SHADER_CAP_GLSL_16BIT_TEMPS for LowerPrecisionTemporaries 
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5746>
 2020-07-07 22:02:06 -04:00
Neil Roberts bb5fc90135 gallium: Add pipe cap for primitive restart with fixed index 
Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the
primitive restart cap for when the hardware can only support the fixed
indices specified in GLES.

The switch statements were automatically modified with this command:

find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \
 -exec sed -i -r \
 's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \
 {} \;

v2: Add a note in screen.rst

Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
 2020-06-22 12:41:56 +00:00
Marek Olšák 1af8fe4ed5 gallium: add shader caps INT16 and FP16_DERIVATIVES 
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5002>
 2020-06-02 20:01:18 +00:00
Marek Olšák 3f1f23239a radeonsi: decrease the max GS invocation count to 32 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Pierre-Eric Pelloux-Prayer 0ee1a724bf gallium: add a new cap PIPE_CAP_GLSL_ZERO_INIT 
Allows driver to select a zero init mode between the 3 possible values.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
 2020-05-05 12:26:02 +02:00
Marek Olšák e58dcc47c3 radeonsi: unify and align down the max SSBO/TBO/UBO buffer binding size 
Rounding down the size fixes:
    KHR-GL45.enhanced_layouts.ssb_member_invalid_offset_alignment

Fixes: 03e2adc990

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
 2020-04-30 22:27:31 +00:00
Marek Olšák 19eb89b0f3 gallium: add PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE for glthread 
and add radeonsi support.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4758>
 2020-04-27 11:56:06 +00:00
Indrajit Kumar Das 133efa112d radeonsi: enable support for AlphaToCoverageDitherControlNV 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
 2020-04-23 12:02:56 +05:30
Timothy Arceri 1f649ff107 radeonsi: don't lower constant arrays to uniforms in GLSL IR 
This re-enables the change made in 2f5783bc2b which was
incorrectly disabled by 3e1dd99adc.

For radeonsi, we will prefer the NIR pass as it'll generate better code
(some index calculation and a single load vs. a load, then index
calculation, then another load) and oftentimes NIR optimization can kick
in and make all the access indices constant.

Fixes: 3e1dd99adc ("radeonsi: Remove a bunch of default handling of pipe caps.")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4474>
 2020-04-08 01:23:40 +00:00
Pierre-Eric Pelloux-Prayer d7008fe46a radeonsi: switch to 3-spaces style 
Generated automatically using clang-format and the following config:

AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlwaysBreakAfterReturnType: None
BasedOnStyle: LLVM
BraceWrapping:
  AfterControlStatement: false
  AfterEnum: true
  AfterFunction: true
  AfterStruct: false
  BeforeElse: false
  SplitEmptyFunction: true
BinPackArguments: true
BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
ForEachMacros:
  - LIST_FOR_EACH_ENTRY
  - LIST_FOR_EACH_ENTRY_SAFE
  - util_dynarray_foreach
  - nir_foreach_variable
  - nir_foreach_variable_safe
  - nir_foreach_register
  - nir_foreach_register_safe
  - nir_foreach_use
  - nir_foreach_use_safe
  - nir_foreach_if_use
  - nir_foreach_if_use_safe
  - nir_foreach_def
  - nir_foreach_def_safe
  - nir_foreach_phi_src
  - nir_foreach_phi_src_safe
  - nir_foreach_parallel_copy_entry
  - nir_foreach_instr
  - nir_foreach_instr_reverse
  - nir_foreach_instr_safe
  - nir_foreach_instr_reverse_safe
  - nir_foreach_function
  - nir_foreach_block
  - nir_foreach_block_safe
  - nir_foreach_block_reverse
  - nir_foreach_block_reverse_safe
  - nir_foreach_block_in_cf_node
IncludeBlocks: Regroup
IncludeCategories:
  - Regex:           '<[[:alnum:].]+>'
    Priority:        2
  - Regex:           '.*'
    Priority:        1
IndentWidth: 3
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
 2020-03-30 11:05:52 +00:00
Kristian H. Kristensen d269fb33b0 radeonsi: Stop exposing PIPE_SHADER_CAP_FP16 
Not fully supported.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4321>
 2020-03-25 22:43:41 +00:00
Marek Olšák 5cc3ab0ba0 vbo,gallium: make glBegin/End buffer size configurable by drivers 
The default is 512 KB, but radeonsi wants 4 MB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4154>
 2020-03-21 03:39:51 +00:00
Marek Olšák 70298ec4c0 gallium: add PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
 2020-03-11 18:45:28 +00:00
Sonny Jiang 5ea2034f58 radeonsi: enable EXT_texture_shadow_lod 
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079>
 2020-03-09 16:08:07 -04:00
Thong Thai 8ab31808fd radeonsi: add 10-bit HEVC encode support for VCN2.0 devices 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4033>
 2020-03-06 16:10:40 +00:00
Eric Anholt 6c10af95c7 radeonsi: Drop PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS. 
Now that we don't expose TGSI, we can stop exposing the flag.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
 2020-01-21 19:04:22 +00:00
Eric Anholt 3e1dd99adc radeonsi: Remove a bunch of default handling of pipe caps. 
u_screen will return 0 for all of these, which means that this is one
less driver to see in git grep when I'm checking who exposes a cap.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3493>
 2020-01-21 19:04:22 +00:00
Marek Olšák 68586bdd21 radeonsi: remove useless #includes 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3399>
 2020-01-15 21:54:55 +00:00
Marek Olšák 420fe1e7f9 radeonsi: remove TGSI 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2020-01-06 15:57:20 -05:00
Thong Thai 466001a226 radeon: Use P010 for decoding of 10-bit videos 
Previously, P016 was used for the decoding of 10-bit HEVC/H.265 encoded
videos, which worked fine for mpv and ffmpeg. GStreamer specifically looks
for P010, so this patch sets the default buffer type to P010 for HEVC
decoding.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3153>
 2020-01-03 16:30:22 +00:00
Marek Olšák 754c7b8939 radeonsi: enable SPIR-V and GL 4.6 for NIR 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-11-27 19:28:35 -05:00
Marek Olšák bda3ec5d55 radeonsi/nir: don't lower fma, instead, fuse fma 
We want fma. This decreases compile times by 4% for Borderlands 2.

48505 shaders in 30515 tests
Totals:
SGPRS: 2206584 -> 2204784 (-0.08 %)
VGPRS: 1647892 -> 1648964 (0.07 %)
Spilled SGPRs: 6256 -> 6078 (-2.85 %)
Spilled VGPRs: 72 -> 72 (0.00 %)
Private memory VGPRs: 2176 -> 2176 (0.00 %)
Scratch size: 2240 -> 2240 (0.00 %) dwords per thread
Code Size: 49680804 -> 49837988 (0.32 %) bytes
LDS: 74 -> 74 (0.00 %) blocks
Max Waves: 371387 -> 371352 (-0.01 %)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-11-15 14:34:49 -05:00
Leo Liu a886ae5162 radeonsi: enable 8K video decode support for HEVC and VP9 
HW 8K decode support starts at Renoir

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
 2019-10-30 12:43:04 -04:00
Marek Olšák 09e0e4c93c gallium: remove PIPE_SHADER_CAP_SCALAR_ISA 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2019-10-10 15:49:19 -04:00
Marek Olšák cebc38ff60 nir: add nir_shader_compiler_options::lower_to_scalar 
This will replace PIPE_SHADER_CAP_SCALAR_ISA.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2019-10-10 15:49:18 -04:00
Marek Olšák 42ea0b7b52 radeonsi: only support at most 1024 threads per block 
LLVM 10 won't support 2048.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-09-09 23:43:03 -04:00
Eric Engestrom 19d9e57f2c amd: replace major llvm version checks with LLVM_VERSION_MAJOR 
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
 2019-09-06 22:26:29 +01:00
Connor Abbott 2f5783bc2b radeonsi/nir: Don't lower constant arrays to uniforms 
shader-db results:

Totals:
SGPRS: 3955968 -> 3954960 (-0.03 %)
VGPRS: 2220220 -> 2220092 (-0.01 %)
Spilled SGPRs: 11387 -> 11325 (-0.54 %)
Spilled VGPRs: 97 -> 97 (0.00 %)
Private memory VGPRs: 2528 -> 2528 (0.00 %)
Scratch size: 2656 -> 2656 (0.00 %) dwords per thread
Code Size: 76002204 -> 75994988 (-0.01 %) bytes
LDS: 740 -> 740 (0.00 %) blocks
Max Waves: 772776 -> 772787 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Totals from affected shaders:
SGPRS: 16840 -> 15832 (-5.99 %)
VGPRS: 16452 -> 16324 (-0.78 %)
Spilled SGPRs: 1416 -> 1354 (-4.38 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 2016 -> 2016 (0.00 %)
Scratch size: 2040 -> 2040 (0.00 %) dwords per thread
Code Size: 953624 -> 946408 (-0.76 %) bytes
LDS: 303 -> 303 (0.00 %) blocks
Max Waves: 1622 -> 1633 (0.68 %)
Wait states: 0 -> 0 (0.00 %)

There were a large number of regressions in code size, but they seem to
be because NIR unrolls some loop which results in the table being
replaced by a bunch of immediates on multiplies etc. -- this bloats code
size since the table size is now included, but means that there are less
loads so it's still a net positive.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2019-09-05 12:39:26 +02:00
Thong Thai 8d03a6b700 radeonsi: add JPEG decode support for VCN 2.0 devices 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
 2019-08-29 17:27:35 -04:00
Ilia Mirkin 958390a9bf gallium/vl: use compute preference for all multimedia, not just blit 
The compute paths in vl are a bit AMD-specific. For example, they (on
nouveau), try to use a BGRX8 image format, which is not supported.
Fixing all this is probably possible, but since the compute paths aren't
in any way better, it's difficult to care.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Fixes: 9364d66cb7 (gallium/auxiliary/vl: Add video compositor compute shader render)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-20 23:51:39 -04:00
Pierre-Eric Pelloux-Prayer f84c9ad17a radeonsi: enable EXT_shader_image_load_store 
This depends on LLVM 10 because this needs https://reviews.llvm.org/D65283

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-06 17:41:07 -04:00
Marek Olšák 91227a1e17 radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-08-06 17:09:02 -04:00
Kenneth Graunke 18c2e09dc7 gallium: Implement GL_EXT_shader_samples_identical via a new capability 
This exposes the textureSamplesIdenticalEXT function in GLSL.

We enable it for iris and radeonsi, because their compilers already
have support for this.  Tested on Intel Kabylake and AMD Vega 64.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-08-01 23:38:54 -07:00