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radeonsi: enable support for AlphaToCoverageDitherControlNV 

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4543>
This commit is contained in:
Indrajit Kumar Das 2020-04-21 16:01:50 +05:30
parent ede36a2efe
commit 133efa112d
3 changed files with 15 additions and 5 deletions
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1
docs/relnotes/new_features.txt
View File

@ -1,6 +1,7 @@
GL_ARB_compute_variable_group_size on i965.
GL_EXT_depth_bounds_test on Iris.
GL_EXT_texture_shadow_lod on radeonsi, nvc0.
GL_NV_alpha_to_coverage_dither_control on radeonsi
GL_NV_copy_image on all gallium drivers.
GL_NV_pixel_buffer_object on all gallium drivers, i915, i965, swrast.
GL_NV_viewport_array2 on nvc0 (GM200+).

1
src/gallium/drivers/radeonsi/si_get.c
View File

@ -160,6 +160,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
case PIPE_CAP_GL_SPIRV:
case PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES:
case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
return 1;
case PIPE_CAP_QUERY_SO_OVERFLOW:

18
src/gallium/drivers/radeonsi/si_state.c
View File

@ -461,11 +461,19 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
color_control |= S_028808_ROP3(0xcc);
}
si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
S_028B70_OFFSET_ROUND(1));
if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
S_028B70_OFFSET_ROUND(1));
} else {
si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
S_028B70_OFFSET_ROUND(0));
}
if (state->alpha_to_coverage)
blend->need_src_alpha_4bit |= 0xf;