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159 Commits

Author SHA1 Message Date
Marek Olšák 99fd408946 radeonsi/gfx11: don't allocate unused wait_mem_scratch 
We sync using PWS instead of memory.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>
 2022-06-15 20:52:42 +00:00
Marek Olšák 98d6a3d6c6 radeonsi/gfx11: don't use memory for waiting for cache flushes 
There is a new flush/wait mechanism called PixelWaitSync that uses
an internal counter.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>
 2022-06-15 20:52:42 +00:00
Pierre-Eric Pelloux-Prayer aa58ff191f Revert "winsys/amdgpu: use AMDGPU_IB_FLAG_PREAMBLE for the CS preamble on gfx10+" 
This reverts commit 8edafaa25c.

This fixes hangs on Navi21.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17032>
 2022-06-15 10:38:04 +00:00
Marek Olšák e4b7088779 radeonsi: allocate only 1 GDS OA counter for gfx10 NGG streamout 
It works with just one.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 0f48c581f9 radeonsi: allocate GDS only once per process 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 091617002f radeonsi: rework how VS_STATE_BITS are set for VS, TES, and GS 
We need more GS/NGG bits, so we need to add current_gs_state for that.
This simplifies the logic in the draw code.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 56359e9f6e radeonsi: remove unused dword from wait_mem_scratch 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 8e0d34ce98 radeonsi: fix uninitialized wait_mem_scratch_tmz 
The initialization was dead code because it's allocated later.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 8edafaa25c winsys/amdgpu: use AMDGPU_IB_FLAG_PREAMBLE for the CS preamble on gfx10+ 
This skips the preamble for following IBs if the queue receives IBs from
the same context back-to-back. This eliminates VGT_FLUSH (for tess and
legacy GS) and PS_PARTIAL_FLUSH (for gfx11) in those cases if the preamble
contains them.

v2: only use this on gfx10+ due to stability issues on Stoney and limited
    testing

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
 2022-06-11 11:14:16 +00:00
Marek Olšák 1fdc3b0fde radeonsi: move CS preamble emission into the winsys 
The preamble will be skipped by the kernel if there is no context switch.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák 32c7805ccc radeonsi: merge all preamble states into one 
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.

The preamble will be passed to the kernel as an IB to execute on a context
switch only.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák a529e4f7ad radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák 39800f0fa3 amd: change chip_class naming to "enum amd_gfx_level gfx_level" 
This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
 2022-05-13 14:56:22 -04:00
Marek Olšák 7203723120 amd: rename RING_* enums to AMD_IP_* 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
 2022-05-10 06:59:55 +00:00
Indrajit Kumar Das 167b378377 radeonsi/gfx11: VRS changes 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
 2022-05-10 04:29:55 +00:00
Marek Olšák ce950f1d96 radeonsi/gfx11: don't use FLUSH_AND_INV_DB_META 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
 2022-05-10 04:29:55 +00:00
Marek Olšák c33a930cea radeonsi/gfx11: emit SQ_NON_EVENT for tessellation at the end of IBs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
 2022-05-10 04:29:55 +00:00
Marek Olšák afc110a1f6 radeonsi/gfx11: implement attributes through memory 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
 2022-05-10 04:29:55 +00:00
Marek Olšák f865631b1b radeonsi: replace SI_RESOURCE_FLAG_UNMAPPABLE with PIPE_RESOURCE_FLAG_UNMAPPABLE 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
 2022-02-22 11:41:04 +00:00
Marek Olšák 18a1af4929 radeonsi: always set FLUSH_ON_BINNING_TRANSITION 
The hardware does the right thing automatically.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
 2022-02-22 11:41:04 +00:00
Shirish S 6f17d8acc9 radeonsi: allocate protected buffer only if required 
protected buffer allocations need to be made if the context is secure

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14848>
 2022-02-03 10:34:12 +01:00
Marek Olšák 61bd8ec043 gallium/radeon: merge BO read/write usage flags with priority flags 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
 2021-10-29 06:54:21 +00:00
Marek Olšák b5cf0d118c gallium/radeon: remove/merge some BO priorities and remove holes 
The upper bits will be used by RADEON_USAGE_*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
 2021-10-29 06:54:21 +00:00
Arvind Yadav 8f9945a75b radeonsi: remove the use of PKT3_CONTEXT_REG_RMW 
This patch is to to remove PKT3_CONTEXT_REG_RMW from radeonsi.
and avoid multiple command buffer(PM4 packet)creation for R_02881C_PA_CL_VS_OUT_CNTL.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12789>
 2021-10-13 10:28:14 +00:00
Marek Olšák fb8f532ea1 radeonsi: implement draw_vertex_state for lower display list overhead 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13050>
 2021-10-01 14:51:23 +00:00
Marek Olšák ccbd551192 radeonsi: disallow NGG fast launch on Navi1x because VGT_FLUSH makes it slower 
This improves viewperf performance on Navi1x.

All Navi1x fast launch workarounds are removed and all fast launch
codepaths are disabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048>
 2021-09-28 17:30:06 +00:00
Marek Olšák e40bd61588 radeonsi: strenthen the ngg->legacy hw workaround, fix fast launch hangs too 
Cc: 20.1 20.2 <mesa-stable@lists.freedesktop.org>

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048>
 2021-09-28 17:30:06 +00:00
Marek Olšák 57bb89fdc5 radeonsi: remove the unused cs parameter from radeon_emit 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13015>
 2021-09-25 08:32:03 +00:00
Marek Olšák edb5fa4d59 radeonsi: eliminate redundant SPI_SHADER_PGM_RSRC3/4_GS register writes 
They don't change much.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
 2021-09-14 15:24:11 +00:00
Marek Olšák 0e64252912 radeonsi: add AMD_DEBUG=ib to print IBs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
 2021-09-10 23:32:03 +00:00
Marek Olšák a2a7610e1f radeonsi: strengthen the VGT_FLUSH condition in begin_new_gfx_cs 
Cc: mesa-stable

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
 2021-09-10 23:32:03 +00:00
Marek Olšák 576f8394db radeonsi: remove the primitive discard compute shader 
It doesn't always work, it's only useful on gfx9 and older, and it's too
complicated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4011

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
 2021-09-10 23:32:03 +00:00
Marek Olšák 9fb77745f5 radeonsi: inline si_need_gfx_cs_space 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
 2021-09-01 00:42:58 +00:00
Marek Olšák 48632778b9 radeonsi: simplify si_need_gfx_cs_space 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
 2021-09-01 00:42:58 +00:00
Marek Olšák b15c413947 radeonsi: simplify memory usage checking by merging vram and gtt counters 
no change in behavior

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
 2021-09-01 00:42:58 +00:00
Yogesh mohan marimuthu 7f9b3a7098 radeonsi: set scratch_state dirty only if ctx->scratch_buffer allocated 
if ctx->scratch_buffer is NULL, then no need to update SPI_TMPRING_SIZE
size register.

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11900>
 2021-07-16 23:08:00 +00:00
Pierre-Eric Pelloux-Prayer 822f377736 radeonsi/gfx7: always sync pfp/me 
Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/4764

Fixes: c5326164 ("radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>
 2021-06-29 23:38:21 +02:00
Marek Olšák 06da711350 radeonsi: remove the GDS variants of compute-based primitive discard 
The GDS ordered append variant is unstable due to kernel and firmware bugs.
The unordered GDS variant isn't faster than the memory-based variant.

Only the memory-based variant is kept.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11510>
 2021-06-28 13:23:14 +00:00
Marek Olšák 24895f020a radeonsi: move a few functions from si_state_draw.cpp into si_gfx_cs.c 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11384>
 2021-06-16 21:29:13 +00:00
Pierre-Eric Pelloux-Prayer 9675de4c18 radeonsi: use si_install_draw_wrapper for tmz handling 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
 2021-06-15 10:19:07 +02:00
Marek Olšák 7844bdadac radeonsi: remove DFSM after we discovered how bad it is 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Marek Olšák 2fad90dc4a radeonsi: implement threaded context callbacks for resource busy checking 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
 2021-05-25 16:15:44 +00:00
Pierre-Eric Pelloux-Prayer a86450e00a radeonsi: avoid querying gpu state if possible 
No-op dispatch should only be setup for full reset, not soft-recovery resets.

The same trick cannot be used in si_get_reset_status because EGL expects
us to return GL_***_CONTEXT_RESET even if it has been fixed by a soft
recovery.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
 2021-04-14 07:00:00 +00:00
Pierre-Eric Pelloux-Prayer 646c5db06f radeonsi: submit cs to failed context instead of skipping them 
Skipping the submission would trigger asserts in debug builds
or cause memory corruption.

Instead the cs is submitted as ususual but the kernel won't submit
it to the hardware (and will return ECANCELED) if the context
is really lost (= not soft-recovered).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2491
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
 2021-04-14 07:00:00 +00:00
Pierre-Eric Pelloux-Prayer aa077ba3a2 radeonsi/rgp: export barriers 
Wrap the si_cp_wait_mem call to emit RGP_SQTT_MARKER_IDENTIFIER_BARRIER_START and
RGP_SQTT_MARKER_IDENTIFIER_BARRIER_END events.

Only for gfx9+ for now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10105>
 2021-04-12 14:27:26 +02:00
Marek Olšák c53261645d radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations 
DCC/CMASK/HTILE clears will not set this. We could do a better job
at not setting this in other cases too

Image copies also don't set this.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
 2021-04-02 12:05:00 +00:00
Marek Olšák 28d065d3e5 radeonsi: don't insert start/stop pipeline stat events if it has no effect 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
 2021-04-02 12:05:00 +00:00
Marek Olšák 230a6dc55d ac,radeonsi: add sampler changes for Aldebaran 
- no 3D and cube textures
- no mipmapping
- no border color
- image_sample is the only supported opcode with a sampler (behaves like _lz)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>
 2021-03-10 18:02:27 +00:00
Pierre-Eric Pelloux-Prayer bddc0e023c radeonsi: fix read from compute / write from draw sync 
A compute dispatch should see the result of a previous draw command.
radeonsi was missing this implicit sync, causing rendering artifacts:
the compute shader was reading from a texture still being written to
by the previous draw.

Framebuffer BOs are marked with RADEON_USAGE_NEEDS_IMPLICIT_SYNC,
so compute jobs will sync.

v2: use RADEON_USAGE_NEEDS_IMPLICIT_SYNC
v3: unconditionally make CB coherent after a flush

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com> (v3)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v3)
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4032
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2878
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1336
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
 2021-02-17 09:11:46 +00:00
Marek Olšák 47587758f2 radeonsi: prefetch VB descriptors right after uploading 
This skips the logic that sets and checks prefetch_L2_mask.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8794>
 2021-01-30 15:41:23 -05:00