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radeonsi: implement threaded context callbacks for resource busy checking 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
This commit is contained in:
Marek Olšák 2021-04-26 21:33:24 -04:00 committed by Marge Bot
parent 9ba17ec21a
commit 2fad90dc4a
3 changed files with 21 additions and 3 deletions
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2
src/gallium/drivers/radeonsi/si_fence.c
View File

@ -470,6 +470,8 @@ static void si_flush_all_queues(struct pipe_context *ctx,
ws->fence_reference(&gfx_fence, sctx->last_gfx_fence);
if (!(flags & PIPE_FLUSH_DEFERRED))
ws->cs_sync_flush(&sctx->gfx_cs);
tc_driver_internal_flush_notify(sctx->tc);
} else {
/* Instead of flushing, create a deferred fence. Constraints:
* - the gallium frontend must allow a deferred flush.

6
src/gallium/drivers/radeonsi/si_gfx_cs.c
View File

@ -93,8 +93,10 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
/* Drop this flush if it's a no-op. */
if (!radeon_emitted(cs, ctx->initial_gfx_cs_size) &&
(!wait_flags || !ctx->gfx_last_ib_is_busy) &&
!(flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION))
!(flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION)) {
tc_driver_internal_flush_notify(ctx->tc);
return;
}
/* Non-aux contexts must set up no-op API dispatch on GPU resets. This is
* similar to si_get_reset_status but here we can ignore soft-recoveries,
@ -198,6 +200,8 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
/* Flush the CS. */
ws->cs_flush(cs, flags, &ctx->last_gfx_fence);
tc_driver_internal_flush_notify(ctx->tc);
if (fence)
ws->fence_reference(fence, ctx->last_gfx_fence);

16
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -761,6 +761,18 @@ fail:
return NULL;
}
static bool si_is_resource_busy(struct pipe_screen *screen, struct pipe_resource *resource,
unsigned usage)
{
struct radeon_winsys *ws = ((struct si_screen *)screen)->ws;
return !ws->buffer_wait(ws, si_resource(resource)->buf, 0,
/* If mapping for write, we need to wait for all reads and writes.
* If mapping for read, we only need to wait for writes.
*/
usage & PIPE_MAP_WRITE ? RADEON_USAGE_READWRITE : RADEON_USAGE_WRITE);
}
static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, void *priv,
unsigned flags)
{
@ -798,8 +810,8 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, v
threaded_context_create(ctx, &sscreen->pool_transfers,
si_replace_buffer_storage,
sscreen->info.is_amdgpu ? si_create_fence : NULL,
NULL,
false,
si_is_resource_busy,
true,
&((struct si_context *)ctx)->tc);
if (tc && tc != ctx && os_get_total_physical_memory(&total_ram)) {