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radeonsi: always set FLUSH_ON_BINNING_TRANSITION 

The hardware does the right thing automatically.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
This commit is contained in:
Marek Olšák 2022-01-21 07:14:26 -05:00 committed by Marge Bot
parent a87ab82f25
commit 18a1af4929
3 changed files with 7 additions and 15 deletions
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1
src/gallium/drivers/radeonsi/si_gfx_cs.c
View File

@ -503,7 +503,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
ctx->last_tes_sh_base = -1;
ctx->last_num_tcs_input_cp = -1;
ctx->last_ls_hs_config = -1; /* impossible value */
ctx->last_binning_enabled = -1;
if (has_clear_state) {
si_set_tracked_regs_to_clear_state(ctx);

1
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -1146,7 +1146,6 @@ struct si_context {
unsigned last_prim;
unsigned last_multi_vgt_param;
unsigned last_gs_out_prim;
int last_binning_enabled;
unsigned current_vs_state;
unsigned last_vs_state;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */

20
src/gallium/drivers/radeonsi/si_state_binning.c
View File

@ -424,20 +424,17 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028C44_BIN_SIZE_X(bin_size.x == 16) | S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) | S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 0));
S_028C44_FLUSH_ON_BINNING_TRANSITION(1));
} else {
radeon_opt_set_context_reg(
sctx, R_028C44_PA_SC_BINNER_CNTL_0, SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2) &&
sctx->last_binning_enabled != 0));
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
}
radeon_end_update_context_roll(sctx);
sctx->last_binning_enabled = false;
}
void si_emit_dpbb_state(struct si_context *sctx)
@ -513,11 +510,8 @@ void si_emit_dpbb_state(struct si_context *sctx)
S_028C44_PERSISTENT_STATES_PER_BIN(sscreen->pbb_persistent_states_per_bin - 1) |
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2) &&
sctx->last_binning_enabled != 1));
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2));
radeon_end_update_context_roll(sctx);
sctx->last_binning_enabled = true;
}