When a blending mode producing "color = src * dst" is used and we
can determine that dst is 1, then the draw call can dropped completely.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Determine if a given shader write the same constant value to its output
if a specific input texture is replaced by constant load.
It's done by checking if the store_output intrinsics only depends on
constant and a texture. If it's true, the given texture is replaced by
a constant load in cloned shader and this clone is optimized.
Then the output is checked (= is it constant or not).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
This allows to implement custom draw_vbo code-path without
touching si_draw_vbo.
As an example, skipped all draw calls with an odd new_draws
could be done like this:
void mywrapper(...) {
if (new_draws % 2)
return;
return sctx->real_draw_vbo(...);
}
if (some_condition_is_met)
si_install_draw_wrapper(sctx, mywrapper);
Instead of having to add the "if ()" condition inside si_draw_vbo.
Note that a single wrapper may be installed so care must be taken
to not override an existing wrapper.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10979>
Instead of N times decrementing the index buffer refcount by 1, decrement
it by N once.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11349>
To make sure the index of global bo table in drm_msm_gem_submit_cmd is
valid at actual submit time.
v1. Move the entry_count calculation into the submit request creation
function.
Fixes: #4877
Fixes: 3f229e34 ("turnip: Implement VK_KHR_timeline_semaphore.")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11260>
This is a port of c111e9099c from iris to
crocus.
Calling SET_TILING on a DMA buffer with the gen12 CCS modifier can fail
unnecessarily. The main surface in the BO is Y-tiled, but the CCS portion is
linear and can have a stride that's not a multiple of 128B. Because SET_TILING
is called on the CCS plane with I915_TILING_Y, the ioctl will sometimes reject
the stride.
SET_TILING was originally used in b6d45e7f74 to
fix an assertion failure in iris_resource_from_handle. Assigning the BO's
tiling_mode field is sufficient to avoid the failure.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11352>
We can't invalidate the range if a buffer is bound for write because we
would need to add the range that is bound, which we don't track.
This fixes buffer mappings incorrectly promoted to unsynchronized because
the valid range was cleared while the buffers were bound for write.
It also clears the valid range if the invalidation is allowed but skipped.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11335>
tc already calculates all the rebinding that needs to be done on a given
context, so (some of) this info can be passed on to drivers to enable
optimizations
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11245>
The test involves timestamping to figure out how long a swap actually
takes, but if anything ends up rescheduling the process you can end up
spuriously failing. I could easily reproduce flakiness by just running a
loop accessing the filesystem in parallel with a loop running the test.
So, it's certainly not usable on a CI system with other piglit tests
running in parallel, and we don't want to run it if it's going to just
produce flake noise.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
This will also give us a central place to handle known CI issues for
piglit.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
The flakiness of this test is due to CI running deqp in parallel, rather
than exposing any underlying driver issue. Just skip it in CI until we
come up with a reasonable way to handle tests to be run in isolation
during a deqp-runner run (likely as part of
https://gitlab.freedesktop.org/anholt/deqp-runner/-/issues/7).
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
I'll watch this for deqp flake reports so we can stay on top of them (and
maybe expire those ancient softpipe annotations at some point).
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
These flake annotations in the skips list predated having flakes support.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
They're too slow to run in CI even on non-tiled renderers, they don't
block conformance (unless you crash), and provide unreliable warning
results unless you isolate them from other activity on the system.
This means that the following jobs now skip these tests:
- deqp-iris-*
- deqp-llvmpipe (you know, the one mentioned in the comment!)
- deqp-virgl-gl
- deqp-zink-lvp
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
The mustpass doesn't have any tests matching these, so no need to
skip. These tests only show up if you run without using a mustpass list.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11333>
When adding crosvm to the x86_test-gl building deqp-runner was also
mistakenly introduced. deqp-runner is already included in the
x86_test-base image.
Additionally, when bumping the deqp-runner version, only the
x86_test-gl tag was updated.
Now, we remove the unnecessary build from x86_test-gl and bump the tag
for the x86_test-base image.
v2:
- Bump x86_test-gl, not x86_test-vk (Tomeu).
v3: add in fixes for duplicated lines in lvp xfails (Anholt)
Fixes: dc9cd18f52 ("ci: Build Crosvm in our container")
Fixes: 53826932db ("ci: Update piglit and deqp/piglit-runner.")
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11359>
The screensaver kicks in at 10 minutes and obscures the screen,
independent of dpms. This causes piglit tests to get flaky (swaps start
taking a whole second, and swapbuffersmsc-divisor-zero times out at
exactly the wrong time) and slow if the run takes longer than 10 minutes.
Hopefully with this we'll see some piglit glx flakes go away forever, it
did seem to for this test locally.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11334>
Trying to run turnip under drm-shim reveals that pretended device
offsets are not sufficiently aligned, failing this assert in tu_pipeline.c:
/* emit program binary & private memory layout
* binary_iova should be aligned to 1 instrlen unit (128 bytes)
*/
assert((binary_iova & 0x7f) == 0);
Round up BO size to 4096 in msm_ioctl_gem_new to avoid this (the kernel
aligns to page size).
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
turnip's DRM device interface requires version 1.6 (for SYNCOBJ).
To unblock use of turnip over drm-shim, raise shim's version to 1.6.
This allows to see shader disassembly, while submission fails with
DRM_SHIM: unhandled core DRM ioctl 0xC4 (0xc01064c4)
TU: error: DRM_IOCTL_SYNCOBJ_RESET failure: Invalid argument
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11331>
If a pipeline enables rasterizerDiscardEnable statically we have to
properly initialize the value, otherwise it won't be updated when a
new pipeline is bound.
Fixes few dEQP-VK.pipeline.extended_dynamic_state.*disable_raster.
Fixes: dd19bf9d7d ("radv: implement dynamic rasterizer discard enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11242>
Report the return code from libdrm instead of errno. While we are at it,
fix the function name in radv_amdgpu_wait_timeline_syncobj().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11269>
That way we can actually import surfaces with modifiers & metadata
planes.
Tested with patches for ffmpeg to use this with kmsgrab & modifiers.
For AMD & multiplanar formats we always have 1 format plane = 1
memory plane, even with modifiers.
Intel (non Gallium) does have 1 format plane is 2 memory planes
for some modifiers with NV12. Currently with Gallium we don't really
have info about layer/plane ordering so this manually orders things
so that they align with Intel.
This shouldn't impact other drivers as without modifiers with metadata
planes this should give equivalent behavior to the old import path.
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10815>
Instead of avoiding out-of-bounds access, avoid creating a load larger
than the original attribute. This should work just as well, since the only
situations expending a load helped was because we shrunk it first.
Also fixes a bug where a 3 component load (4 components with the first
component skipped) would be incorrectly expanded to 4 components because
the stride check would never be performed. Maybe we should avoid skipping
the first component in some situations, but I'm not sure if it's worth
the VGPR cost.
fossil-db (vega10):
Totals from 583 (0.39% of 149974) affected shaders:
CodeSize: 1496848 -> 1500868 (+0.27%); split: -0.03%, +0.30%
Instrs: 286155 -> 286575 (+0.15%); split: -0.07%, +0.22%
Latency: 2947101 -> 2946865 (-0.01%); split: -0.23%, +0.22%
InvThroughput: 797396 -> 797127 (-0.03%); split: -0.08%, +0.04%
fossil-db (polaris10):
Totals from 583 (0.39% of 151365) affected shaders:
SGPRs: 38880 -> 39216 (+0.86%)
VGPRs: 24440 -> 24356 (-0.34%)
CodeSize: 1506808 -> 1510876 (+0.27%); split: -0.01%, +0.28%
Instrs: 288735 -> 289167 (+0.15%); split: -0.06%, +0.21%
Latency: 2963263 -> 2961884 (-0.05%); split: -0.24%, +0.19%
InvThroughput: 802351 -> 801665 (-0.09%); split: -0.12%, +0.04%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9007>
Daniel Stone
Pierre-Eric Pelloux-Prayer
Marek Olšák
Hyunjun Ko
Dave Airlie
Dave Airlie
Andres Gomez
Mike Blumenkrantz
Michel Zou
Emma Anholt
Alexander Monakov
Rhys Perry
Samuel Pitoiset
Bas Nieuwenhuizen