Commit Graph

38 Commits

Author SHA1 Message Date
Leo Liu c836f2ce28 radeon/uvd: adapt gfx9 surface to uvd
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30 14:44:33 +02:00
Marek Olšák ba2e7c68ce gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Christian König 88f3451083 radeon/uvd: enable 10bit HEVC decode v2
Just use whatever the state tracker allocated.

v2: fix msb mode

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13 08:51:29 +01:00
Marek Olšák 69f489dfa1 radeonsi: use SDMA in rvid_buffer_clear on CIK-VI
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-05 18:43:23 +01:00
Marek Olšák 29144d0f34 gallium/radeon: stop using PIPE_BIND_CUSTOM
it has no effect whatsoever

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák 2a2e537577 gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment
these names were misleading.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Nicolai Hähnle 13cb41f666 radeon/video: don't use sub-allocated buffers
Cc: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:29 +02:00
Christian König 36df04dac4 radeon/uvd: move polaris fw check into radeon_video.c v2
It's actually not very clever to claim to support H.264
and then fail to create a decoder.

v2: prefix FW macro with UVD_.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:31 +02:00
Christian König 5290bf43c8 radeon/video: fix coding style in radeon_video.c v2
v2: fix other tabs as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:31 +02:00
Marek Olšák d5383a7d31 gallium/radeon: use r600_resource_reference
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-06-25 23:13:42 +02:00
Christian König b3e75c3997 radeon/uvd: fix the H264 level for Tonga v2
We support 5.2 for a while now.

v2: we even support 5.2 for H264, 5.1 is for HEVC.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>
2016-06-02 09:27:57 +02:00
Jan Vesely 47b390fe45 Treewide: Remove Elements() macro
Signed-off-by: Jan Vesely <jano.vesely@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-17 15:28:04 -04:00
Marek Olšák f564b61d33 radeonsi: rework clear_buffer flags
Changes:
- don't flush DB for fast color clears
- don't flush any caches for initial clears
- remove the flag from si_copy_buffer, always assume shader coherency

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-04-28 20:16:56 +02:00
Nicolai Hähnle 562c4a17b7 winsys/radeon: remove use_reusable_pool parameter from buffer_create
All callers set this parameter to true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-27 11:16:41 -05:00
Nicolai Hähnle c868974396 radeon/video: always use the reusable buffer pool
A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
cache _shouldn't_ be used, just use the cache always.

Cc: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-27 11:16:41 -05:00
Boyuan Zhang 06c862d67d radeon/video: enable HEVC main 10 decode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-11 22:33:56 -05:00
Tamil velan 353a4f844f radeon/uvd: increase max height to 4096 for VI and newer
With this issue 'mpv --hwdec=vdpau --vo=vdpau <stream>' fails
for vdpau decode if the stream height is 4096. Vdpau decode of
height upto 4096 is necessary usecase on amdgpu driver for VI
and newer platforms.

The fix is in driver specific implementation of "Decoder
Query Capabilities" API to return 4096 for VI and newer
platforms. With this fix vdpauinfo reports height support as
4096 and mpv for vdpau decode works fine for 4096 height streams.

Signed-off-by: Tamil velan <Tamil-Velan.Jayakumar@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-08 19:01:19 -05:00
Christian König e148a3b6e9 radeon/uvd: disable MPEG1
The hardware simply doesn't support that correctly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-03-08 12:57:08 +01:00
Marek Olšák cf811faeff gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Boyuan Zhang 6bad554d98 radeon/uvd: fix VC-1 simple/main profile decode v2
We just needed to set the extra width/height fields to get this working.

v2 (chk): rebased, CC stable added, commit message added, fixed coding style

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-11-06 20:07:23 +01:00
Alex Deucher 7b63658125 radeon/uvd: don't expose HEVC on old UVD hw (v3)
The section for UVD 2 and older was not updated
when HEVC support was added. Reported by Kano
on irc.

v2: integrate the UVD2 and older checks into the
main switch statement.
v3: handle encode checking as well.  Encode is
already checked in the top case statement, so
drop encode checks in the lower case statement.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-10-22 16:22:44 -04:00
Boyuan Zhang 839bf82606 radeon/uvd: implement HEVC support
add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.

v2: disable interlace for HEVC
    add CZ sps flag workaround
    fix coding style

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-08-14 15:02:31 +02:00
Leo Liu 4dfcf6e3a9 radeon/video: config encode stacked frame number based on HW
since VCE 3.0 with dual instances, we need stack frames for them.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu c29f0d4722 radeon/video: add 4K support for decode/encode parameters
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Marek Olšák a582b22c63 winsys/radeon: add a private interface for radeon_surface 2015-04-29 21:51:40 +02:00
Marek Olšák dcfbc006b6 winsys/radeon: move radeon_winsys.h to drivers/radeon 2015-04-29 21:51:40 +02:00
Marek Olšák edf18da85d radeonsi: only flush the right set of caches for CP DMA operations
That's either framebuffer caches or caches for shader resources.
The motivation is that framebuffer caches need to be flushed very rarely
here.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-01-07 12:06:43 +01:00
Christian König 4dfdcdb4b3 radeon/video: use the hw to initial clear the buffers
Less CPU overhead and avoids contention over CPU accessible memory on startup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:06:03 +02:00
Christian König 4bc0059229 radeon/video: use more of the common buffer code v2
In preparation to using buffers clears with the hw engine(s).

v2: split out flipping to using hw buffer clears.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:05:55 +02:00
Emil Velikov a131263a2f gallium/radeon: cleanup header inclusion
- Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}.
 - Remove top_srcdir/src/gallium/drivers/radeon from the includes.

As a result:
 - Common radeon headers are prefixed with 'radeon/'
 - Winsys header inclusion is prefixed 'radeon/drm'

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-28 21:24:37 +01:00
Alex Deucher 6b48c18b03 radeon/uvd: remove comment about RV770
It doesn't seem to support field based decode after testing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-08-27 10:04:13 -04:00
Christian König 80771e47b6 radeon/uvd: fix field handling on R6XX style UVD
The first UVD generation can only do frame based output.

Signed-off-by: Christian König <christian.koenig@amd.com>
2014-08-26 17:56:57 +02:00
Michel Dänzer 07c65b85ea r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-07-23 18:55:50 +09:00
Grigori Goronzy 6cd30f5d73 radeon/uvd: disable VC-1 simple/main on UVD 2.x
It's about as broken as on later UVD revisions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66452
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-06-18 13:58:52 +02:00
Christian König 9ff0cf903d radeon/vce: initial VCE support v8
v2 (chk): revert feedback buffer hack
v3 (slava): fixed bitstream size calculation
v4 (chk): always create buffers in the right domain
v5 (chk): flush async
v6 (chk): rework fw interface add version check
v7 (leo): implement cropping support
v8 (chk): add hw checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
2014-02-13 11:11:24 +01:00
Christian König ee978aee94 vl: add H264 encoding interface
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
2014-02-11 13:26:13 +01:00
Christian König 9b218dcdd7 radeon/video: directly create buffers in the right domain
Avoid moving things around on start of stream.

Signed-off-by: Christian König <christian.koenig@amd.com>
2014-02-06 15:54:14 +01:00
Christian König 7bcfb0bc8f radeon/video: seperate common video functions
Signed-off-by: Christian König <christian.koenig@amd.com>
2014-02-06 15:54:13 +01:00