Commit Graph

119073 Commits

Author SHA1 Message Date
Marek Olšák 3c265c2586 radeonsi: rename dma_cs -> sdma_cs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:33 -05:00
Marek Olšák cd6a4f7631 radeonsi: add AMD_DEBUG=nodmacopyimage for debugging
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:32 -05:00
Marek Olšák 0c9e7a67f9 radeonsi: add AMD_DEBUG=nodmaclear for debugging
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:30 -05:00
Marek Olšák 4110e6e564 radeonsi: remove broken and unused SI SDMA image copy code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:28 -05:00
Marek Olšák 503bd821fa radeonsi: rename SDMA debug flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:11 -05:00
Tomeu Vizoso d62dd8b0cb gitlab-ci: Switch LAVA jobs to use shared dEQP runner
Take one step towards sharing code between the LAVA and non-LAVA jobs,
with the goals of reducing maintenance burden and use of computational
resources.

The env var DEQP_NO_SAVE_RESULTS allows us to skip the procesing of the
XML result files, which can take a long time and is not useful in the
LAVA case as we are not uploading artifacts anywhere at the moment.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2020-01-06 14:27:36 +01:00
Tomeu Vizoso f5c2807ff2 gitlab-ci: Update kernel for LAVA to 5.5-rc1 plus fixes
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2020-01-06 14:27:21 +01:00
Alyssa Rosenzweig b3ff83c107 panfrost: Handle PIPE_FORMAT_R10G10B10A2_USCALED
Same format code as UINT... might be different in how it's fed into a
shader but we'll deal with that when we get there.

Fixes dEQP-GLES3.functional.vertex_arrays.single_attribute.output_types.usigned_int2_10_10_10.components4_vec2_quads1

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:50:00 -05:00
Alyssa Rosenzweig 5c71547c68 panfrost: Report MSAA 4x supported for dEQP
Fixes dEQP-GLES3.functional.state_query.integers.max_samples_getinteger64

We'll have to actually implement multisampling next, but hey.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:58 -05:00
Alyssa Rosenzweig 32851ff715 panfrost: Cleanup tiling selection logic
Make it a lot more obvious what we're doing and fix more than a few
corner cases in the process.

Fixes
dEQP-GLES3.functional.buffer.map.write.render_as_index_array.pixel*, and
likely others.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:53 -05:00
Alyssa Rosenzweig dadfca3775 panfrost: Implement sRGB blend shaders
We use the lowering in nir_format_convert. There are native ops for this
so this is far from optimal and not remotely efficient but as with most
blend shader things right now, it's hard enough to get it working, so
let's focus on that for now. We'll make it fast later (once we have
GLES3 stable, we can start optimizing these things).

Fixes dEQP-GLES3.functional.fragment_ops.blend.fbo_srgb.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:48 -05:00
Alyssa Rosenzweig ef00849877 panfrost: Support rendering to non-zero Z/S layers
Fixes abort in STK's shadow implementation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:42 -05:00
Alyssa Rosenzweig ef8c2ebee1 panfrost: Texture from Z32F_S8 as R32F
Z32F_S8 becomes Z32F in texturing, which in turn just becomes R32F.

Fixes dEQP-GLES3.functional.texture.format.sized.*.depth32f_stencil8*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2020-01-06 07:49:33 -05:00
Danylo Piliaiev f3ca47d9f3 iris/query: Implement PIPE_QUERY_GPU_FINISHED
Implementation is similar to radeonsi in 5f1cef76

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-06 12:43:14 +02:00
Erik Faye-Lund 642125edd9 st/mesa: use uint-samplers for sampling stencil buffers
Otherwise, we end up mismatching the sampler types when rendering.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-06 09:23:43 +01:00
Samuel Pitoiset 09ea2de2b8 ac/surface: use uint16_t for mipmap level pitches
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-06 07:59:50 +01:00
Jonathan Marek 680d806950 etnaviv: fix incorrectly failing vertex size assert
Changes the assert to match the comment above.

This assert was failing in some cases while running darkplaces.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-05 17:04:39 +00:00
Vasily Khoruzhick c5ae64ebc7 lima: fix PP stream terminator size
PP stream terminator size seems to be 4 words, it worked with full PP
stream because we align stream beginning to 32 bytes and BO is
initialized with zeroes. But with partial PP stream it sometimes break
if for new PP stream we reuse BO that has non-zero value at this place.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:39 -08:00
Vasily Khoruzhick 4f5bfe2a5e lima: don't reload and redraw tiles that were not updated
We don't need to reload and redraw some tiles if framebuffer was not
cleared and scissor test was enabled for some of draws. This simple
optimization fixes cursor lag in X11

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:36 -08:00
Vasily Khoruzhick 83abdf8e45 lima: postpone PP stream generation
This commit postpones PP stream generation till job is submitted.
Doing that this late allows us to skip reloading and redrawing tiles
that were not updated.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2020-01-05 00:16:33 -08:00
Andreas Baierl 7ad1896ab8 lima/parser: Fix VS cmd stream parser
prefetch is int, not bool.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-05 03:08:01 +00:00
Andreas Baierl af7dc4675d lima/parser: Fix rsw parser
Drop assert as it is not necessary and used wrong anyway.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
2020-01-05 03:08:01 +00:00
Kenneth Graunke defb3a9465 anv: Only enable EWA LOD algorithm when doing anisotropic filtering.
Updated documentation renames "Anisotropic Algorithm" to "LOD Algorithm"
and adds a note for Gen9+ saying "The EWA Algorithm should only be
enabled for Anisotropic Filtering modes." and indicating that the extra
accuracy shouldn't be necessary for other modes, and comes at a cost.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-04 14:27:22 -08:00
Kenneth Graunke c0c899cf78 iris: Allow HiZ for copy_region sources
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2020-01-04 12:25:55 -08:00
Jason Ekstrand 7d75bf4f3f i965: Allow HiZ for glCopyImageSubData sources
v2 (Ken): Handle platforms without sampler support for HiZ

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v2 changes]
2020-01-04 12:25:55 -08:00
Jason Ekstrand 52ad1712ed anv: Allow HiZ in TRANSFER_SRC_OPTIMAL on Gen8-9
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand b274469daa intel/blorp: Use the source format when using blorp_copy with HiZ
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand ea7446ba82 i965/blorp: Don't resolve HiZ unless we're reinterpreting
This eliminates 50% of pixels (2M) rendered for a blit in GS:GO.  This
accounts for 3% of pixels rendered in the game.  Total GPU clocks for
the first 900 frames of CSGO improves by 1%.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand 95cc5438eb blorp: Allow reading with HiZ
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Jason Ekstrand 4a1093005c blorp: Stop whacking Z24 depth to BGRA8
The shader code required to do this is int(sat(x) * UINT24_MAX) which
isn't really worth all the effort to avoid.  Doing the format
conversion, on the other hand, prevents us from sampling with HiZ which
is something that we very much want on gen8-9 where we can.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2020-01-04 12:25:54 -08:00
Christian Gmeiner a597a64ae2 etnaviv: move descriptor based texture structs
This moves the descriptor based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-04 20:44:36 +01:00
Christian Gmeiner 7c687d221d etnaviv: move state based texture structs
This moves the state based texture structs and their helpers
into the only user.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2020-01-04 20:44:36 +01:00
Roman Stratiienko ed0fa78b46 panfrost: Fix Android build
Include missing `encoder/pan_props.c` into the build.

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2020-01-04 16:54:38 +00:00
Gert Wollny 9162e2f03f mesa/st: glsl_to_nir: don't lower atomics to SSBOs if driver supports HW atomics
At least on r600 HW atomic operations are way less expensive than SSBO atomic
operations.

v2: use st->has_hw_atomics (Erik Anholt)

v3: remove second invocation of atomic to ssbo lowering (Erik Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny b119f8b4a0 r600: Delete vertex buffer only if there is actually a shader state
Fixes: gl-2.0-vertexattribpointer
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny 32bb5f2941 r600: Make SID and unsigned value
The value is never negative, and makeing it unsigned fixes some
warnings

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny e8559ae448 r600: Fix maximum line width
There are only 13 bits available to store the line width, hence
it can't be larger than 8191

v2: Add Fixes tag

v3: - Unify value since for all r600 archs (Konstantin Kharlamov)
    - Correct the value the line width value is emitted as a 12.4
      fixed point value of 1/2 line width on r600-r700 and as
      8 * line width on Evergreen and newer.

Fixes: 06bfb2d28f
    r600: fork and import gallium/radeon

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny 829107819d r600/sb: Correct SB disassambler for better debugging
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny bfbdaf9a46 r600: Make it possible to include r600_asm.h in a C++ file
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny 23c5ba8baa r600: Add functions to dump the shader info
This will be helpful to compare TGSI and NIR code path,

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Konstantin Kharlamov <hi-angel@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny 570a6c6c79 gallium: tgsi_from_mesa - handle VARYING_SLOT_FACE
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny 6c9495b392 nir: make nir_get_texture_size/lod available outside nir_lower_tex
This functions can be useful in other places.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Gert Wollny f69bf7fe8c gallium/tgsi_from_mesa: Add 'extern "C"' to be able to include from C++
The r600/nir backend is in C++ and needs to include this file.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3286>
2020-01-04 16:22:40 +00:00
Bas Nieuwenhuizen 96c9483ccf spirv: Fix glsl type assert in spir2nir.
Fixes: 624789e370 "compiler/glsl: handle case where we have multiple users for types"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2020-01-04 15:53:24 +00:00
Christian Gmeiner b178262cb9 etnaviv: use a better name for FE_VERTEX_STREAM_UNK14680
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2020-01-04 14:15:36 +01:00
Bas Nieuwenhuizen 17741a0a05 radv: Only use the gfx mipmap level offset/pitch for linear textures.
The tiled-case is non-sensical for non-base mips, but Vulkan requires
that this function handles it but at the same time does not require
returning anything useful. So we can basically return anything.

Correct tiled pitch and offset are still required for our own WSI and
in the future getting the layouts of images with DRM format modifiers.
Both don't have to deal with images with more than 1 level though.

Fixes: 824bd0830e "radv: return the correct pitch for linear mipmaps on GFX10"
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2301
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2304
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-04 13:04:40 +01:00
Bas Nieuwenhuizen f0ed67b770 Revert "amd/common: Always initialize gfx9 mipmap offset/pitch."
This reverts commit 973181c06c.

Requested by Marek.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-04 13:04:40 +01:00
Kenneth Graunke 645b195312 iris: Delete remnants of the unimplemented ASTC 5x5 workaround
I copy and pasted some of the boilerplate but never the implementation.
For now, ASTC 5x5 is disabled and faked via uncompressed RGBA; let's
delete these remnants until such a time when we implement it properly.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-03 18:06:38 -08:00
Kenneth Graunke e858321f09 iris: Disable ASTC 5x5 support on Gen9 for now.
Intel Gen9 hardware has some nasty restrictions where ASTC 5x5 formats
and color compression can't both live in the sampler cache at the same
time.  To properly support it, we have to track which of those exist
in the cache and flush ASTC out or resolve away compression.

As far as I'm aware, very little uses ASTC 5x5 textures, so instead
of replicating all that for iris, we simply turn it off and rely on
the Gallium fallback mechanism to fake it via uncompressed RGBA.

This should avoid GPU hangs any time people use ASTC 5x5 with CCS.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2020-01-03 18:06:38 -08:00
Kenneth Graunke 8e6308363b st/mesa: Allow ASTC5x5 fallbacks separately from other ASTC LDR formats.
This patch allows us to fake ASTC 5x5 specifically, while leaving the
other ASTC LDR formats with native support.  I plan to use this in iris,
at least for the time being.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2020-01-03 18:06:35 -08:00