Commit Graph

111234 Commits

Author SHA1 Message Date
Mathias Fröhlich 1d0a8cf40d mesa: Prevent classic swrast crash on a surfaceless context v2.
This fixes the egl_mesa_platform_surfaceless piglit test as well
as the new egl_ext_device_base piglit test on classic swrast.

v2: Fix swrast surfaceless contexts on the driver side.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-28 08:27:16 +02:00
Samuel Pitoiset 15cb19ed6f radv add radv_get_resolve_pipeline() in the compute path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-28 08:17:26 +02:00
Samuel Pitoiset 469258c3b1 radv: cleanup the compute resolve path for subpass
This makes use of radv_meta_resolve_compute_image() by filling
a VkImageResolve region instead of duplicating code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-28 08:17:23 +02:00
Timothy Arceri d2b0246741 radeonsi: add drirc workaround for American Truck Simulator
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110711
2019-05-28 08:47:44 +10:00
Timothy Arceri 11e16ca7ce Revert "st/mesa: expose 0 shader binary formats for compat profiles for Qt"
This reverts commit 55376cb31e.

It's been over a year and both QT 5.9.5 and 5.11.0 contained a fix for the
original issue. It seems i965 only ever applied this workaround to the
18.0 branch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-28 08:46:50 +10:00
Lionel Landwerlin 2042f22e28 anv: fix apply_pipeline_layout pass for arrays of YCbCr descriptors
When using the binding tables to access arrays of YCbCr descriptors we
did not consider the offset of the accessed element. We can't do a
simple multiple because the binding table entries are tightly packed.

For example element 0 of the array could use 2 entries/planes and
element 1 could use 2 entries/planes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bb8768b9d ("anv: toggle on support for VK_EXT_ycbcr_image_arrays")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-05-27 22:47:53 +01:00
Marek Olšák fccced57cf radeonsi: clean up winsys creation
- unify the code
- choose radeon or amdgpu based on the DRM version, not based on which one
  succeeds first
2019-05-27 15:26:06 -04:00
Marek Olšák bb5d82bd06 radeonsi: allow query functions for compute-only contexts 2019-05-27 15:26:06 -04:00
Marek Olšák b257956021 ac: treat Mullins as Kabini, remove the enum
it's the same design
2019-05-27 15:10:51 -04:00
Christian Gmeiner 37af75f88c etnaviv: rs: choose clear format based on block size
Fixes following piglit and does not introduce any regressions.
  spec@ext_packed_depth_stencil@fbo-depth-gl_depth24_stencil8-blit

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2019-05-27 20:55:11 +02:00
Vasily Khoruzhick af0de6b91c lima/ppir: implement discard and discard_if
This commit also adds codegen for branch since we need it
for discard_if.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-05-27 07:39:03 -07:00
Samuel Pitoiset 7a7be61398 radv: ignore the loadOp if the first use of an attachment is a resolve
Based on ANV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:39 +02:00
Samuel Pitoiset ff27eb509a radv: always dirty the framebuffer when restoring a subpass
The old code was not wrong because the transitions performed
after the resolves should re-emit the framebuffer if needed.

This change is mostly a no-op but it improves consistency
regarding other meta operations that need to save/restore subpasses.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:36 +02:00
Samuel Pitoiset 9af15986b0 radv: add radv_clear_htile() helper
This helper will be useful for clearing HTILE after some
depth/stencil resolves.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 13:52:34 +02:00
Chenglei Ren 13b38ca1e4 anv/android: fix missing dependencies issue during parallel build
The libmesa_anv_gen* modules require anv_extensions.h, patch makes sure
it gets generated as a dependency before building them.

Signed-off-by: Chenglei Ren <chenglei.ren@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
2019-05-27 10:13:17 +03:00
Samuel Pitoiset 2d2e7954c3 radv: tidy up GetQueryPoolResults for occlusion queries
Just move the block that checks the availability bit into the
switch like other query types.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-27 08:50:55 +02:00
Kenneth Graunke b5fa3abfc2 iris: Don't flag IRIS_DIRTY_URB after BLORP operations unless it changed
We already flag IRIS_DIRTY_URB when we change it, but we were
additionally flagging it on every BLORP operation, even if we didn't.
2019-05-26 17:45:18 -07:00
Dave Airlie 7fe5a8e874 Revert "mesa: unreference current winsys buffers when unbinding winsys buffers"
This reverts commit 12bf7cfecf.

This commits caused lots of problems:
https://bugs.freedesktop.org/show_bug.cgi?id=110721
https://bugs.freedesktop.org/show_bug.cgi?id=110761

Fixes: 12bf7cfecf ("mesa: unreference current winsys buffers when unbinding winsys buffers")
Pushing without review as we need to get it into next stable.
2019-05-27 09:36:28 +10:00
Alyssa Rosenzweig 659aa3dd65 panfrost/midgard: Implement fneg/fabs/fsat
Fix a regression I inadvertently caused by acking typeless movs before
implementing/pushing this *whistles*

Nothing to see here, move along folks.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-26 03:16:37 +00:00
Qiang Yu 1dc593e9b9 lima: fix lima_blit with non-zero level source resource
lima_blit will do blit between resources with different levels.
When blit from a level!=0 source, it will sample from that level
of resource as texture.

Current texture setup won't respect level when not mipmap filter.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-25 12:41:44 +08:00
Qiang Yu 54490b0b36 lima: fix render to non-zero level texture
Current implementation won't respect level of surface to render.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-25 12:41:31 +08:00
Dylan Baker 9838185056 editorconfig: Fix meson style
The syntax was wrong, resulting in it not working at all.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-05-24 18:44:18 +00:00
Chia-I Wu ea1e0acfd0 virgl: remove an incorrect check in virgl_res_needs_flush
Imagine this

  resource_copy_region(ctx, dst, ..., src, ...);
  transfer_map(ctx, src, 0, PIPE_TRANSFER_WRITE, ...);

at the beginning of a cmdbuf.  We need to flush in transfer_map so
that the transfer is not reordered before the resource copy.  The
check for "vctx->num_draws == 0 && vctx->num_compute == 0" is not
enough.  Removing the optimization entirely.

Because of the more precise resource tracking in the previous
commit, I hope the performance impact is minimized.  We will have to
go with perfect resource tracking, or attempt a more limited
optimization, if there are specific cases we really need to optimize
for.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Chia-I Wu 56f9b60e50 virgl: reemit resources on first draw/clear/compute
This gives us more precise resource tracking.  It can be beneficial
because glFlush is often followed by state changes.  We don't want
to reemit resources that are going to be unbound.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Chia-I Wu 424ec2356b virgl: add missing emit_res for SO targets
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-05-24 17:37:40 +00:00
Roland Scheidegger d4e8a44bf6 gallivm: fix default cbuf info.
The default null_output really needs to be static, otherwise the values
we'll eventually get later are doubly random (they are not initialized,
and even if they were it's a pointer to a local stack variable).
VMware bug 2349556.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-05-24 19:22:50 +02:00
Roland Scheidegger 84f3f1cf00 scons: fix build with llvm 9.
The x86asmprinter component is gone, and things seem to work by just
removing it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110707

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-05-24 18:28:28 +02:00
Tomeu Vizoso 9fe1a925e2 panfrost: Dereference sampled texture
We are currently leaking resources if they were sampled from. Once we
are done with a sampler, we should dereference that resource.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 16:50:09 +02:00
Tomeu Vizoso 3c81010213 panfrost: ci: Avoid pulling Docker image on every run
Jump over the container stage if we haven't changed any of the files
that involved in building the container images.

This saves 1-2 minutes in each run and helps conserve resources.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 16:50:09 +02:00
Jason Ekstrand f2dc0f2872 nir: Drop imov/fmov in favor of one mov instruction
The difference between imov and fmov has been a constant source of
confusion in NIR for years.  No one really knows why we have two or when
to use one vs. the other.  The real reason is that they do different
things in the presence of source and destination modifiers.  However,
without modifiers (which many back-ends don't have), they are identical.
Now that we've reworked nir_lower_to_source_mods to leave one abs/neg
instruction in place rather than replacing them with imov or fmov
instructions, we don't need two different instructions at all anymore.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
2019-05-24 08:38:11 -05:00
Jason Ekstrand 22421ca7be nir/builder: Merge nir_[if]mov_alu into one nir_mov_alu helper
Unless source modifiers are present, fmov and imov are the same.
There's no good reason for having two helpers.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand cd73b6174b nir/lower_to_source_mods: Stop turning add, sat, and neg into mov
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand 2a39788d03 nir/source_mods: Add a helpers for setting source modifiers
It's potentially a tiny bit less efficient but the helpers make it much
easier to sort out the rules for updating source modifiers.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand 8ffbb54405 intel: Implement abs, neg, and sat in the back-end
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand 4fde459563 intel/nir: Call alu_to_scalar one last time before out-of-ssa
A few of our very late passes can end up generating vectors accidentally
so we need to get rid of them.  The only known case of this is the ffma
peephole which generates fneg and fabs as vectors.  Currently, they're
not a problem because they get turned into fmov which the back-end
compiler knows how to handle as a vector.  That's about to change.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand ddd08e1888 nir/builder: Remove the use_fmov parameter from nir_swizzle
This flag has caused more confusion than good in most cases.  You can
validly use imov for floats or fmov for integers because, without source
modifiers, neither modify their input in any way.  Using imov for floats
is more reliable so we go that direction.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Jason Ekstrand 6c2ca2a5d3 ptn,ttn: Use nir_channel for selecting channels
Both of these passes predate the nir_channel helper.  We should just use
it instead of hand-rolling it in both passes.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-24 08:38:11 -05:00
Michel Zou 88eb2a1f7e scons: For MinGW use -posix flag.
Signed-off-by: Jose Fonseca <jfonseca@vmware.com>
2019-05-24 12:18:40 +01:00
Christian Gmeiner 78fb5594be etnaviv: use the correct uniform dirty bits
Found during code inspection.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-05-24 12:41:43 +02:00
Danylo Piliaiev c82dcf89ae anv: Do not emulate texture swizzle for INPUT_ATTACHMENT, STORAGE_IMAGE
If descriptorType is VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
or VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT, the imageView member of each
element of pImageInfo must have been created with the identity swizzle.

Fixes: d2aa65eb

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-24 09:20:38 +00:00
Tapani Pälli 397fe0cc50 st/dri: enable EGL_ANDROID_blob_cache on gallium drivers
Verified to work properly with Iris driver on Android Celadon. Cache
files get generated as 'com.android.opengl.shaders_cache' for each
application.

v2: check that cache was returned (Eric Engestrom)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-05-24 09:17:04 +03:00
Alyssa Rosenzweig ea6b581444 panfrost: Remove the standalone compiler
Now that the online compiler and pandecode are reliable and upstreamed,
nobody is using this. If somebody does need it, it should be easy enough
to bring back, I suppose. At the moment, it's just a maintenance hazard,
since meson is silly and does double builds for compiler updates (triple
for disassembler changes).

If people need the standalone _disassembler_, that can be added
trivially into pandecode (pandecode already includes the disassembler).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-24 03:10:43 +00:00
Eric Engestrom 8d386e6eef vk/util: suppress warning about out-of-enum android value
src/vulkan/util/vk_enum_to_str.c: In function ‘vk_structure_type_size’:
src/vulkan/util/vk_enum_to_str.c:3335:9: warning: case value ‘1000010000’ not in enumerated type ‘VkStructureType’ {aka ‘const enum VkStructureType’} [-Wswitch]
         case VK_STRUCTURE_TYPE_NATIVE_BUFFER_ANDROID: return sizeof(VkNativeBufferANDROID);
         ^~~~

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-23 15:28:43 +00:00
Kenneth Graunke 25afbb04c2 iris: Advertise coherent framebuffer fetches
This lets us advertise GL_EXT_shader_framebuffer_fetch and
GL_KHR_blend_equation_advanced_coherent support.
2019-05-23 08:13:10 -07:00
Kenneth Graunke cca8af0c7d gallium: Add PIPE_CAP_FBFETCH_COHERENT and expose extensions
st/mesa now exposes KHR_blend_equation_advanced_coherent and
EXT_shader_framebuffer_fetch if the new capability is supported.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-23 08:13:09 -07:00
Kenneth Graunke 87f4286137 st/mesa: Advertise GL_EXT_shader_framebuffer_fetch_non_coherent
This extension requires the ability to read from all render targets,
so we only enable it if PIPE_CAP_FBFETCH >= PIPE_CAP_MAX_RENDER_TARGETS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-23 08:13:09 -07:00
Kenneth Graunke a2d7834457 gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH count
TGSI's FBFETCH instruction currently only supports reading from a single
render target, but NIR intrinsics can support multiple render targets.

radeonsi can only support fetching from RT 0, but other drivers may be
able to support fetching from any render target.

To express this, this patch renames PIPE_CAP_TGSI_FS_FBFETCH to simply
PIPE_CAP_FBFETCH, and converts it from a boolean "is FBFETCH supported?"
to an integer number of render targets which can be fetched.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-23 08:13:07 -07:00
Kenneth Graunke 7d2b54e393 iris: Record state sizes for INTEL_DEBUG=bat decoding.
Felix noticed a crash when using INTEL_DEBUG=bat decoding.  It turned
out that we were sometimes placing variable length data near the end
of a buffer, and with the decoder guessing random lengths rather than
having an actual count, it was walking off the end and crashing.  So
this does more than improve the decoder output.

Unfortunately, this is a bit more complicated than i965's handling,
because we don't have a single state buffer.  Various places upload
data via u_upload_mgr, and so there isn't a central place to record
the size.  We don't need to catch every single place, however, since
it's only important to record variable length packets (like viewports
and binding tables).

State data also lives arbitrarily long, rather than being discarded on
every batch like i965, so we don't know when to clear out old entries
either.  (We also don't have a callback when an upload buffer is
released.)  So, this tracking may space leak over time.  That's probably
okay though, as this is only a debugging feature and it's a slow leak.
We may also get lucky and overwrite existing entries as we reuse BOs,
though I find this unlikely to happen.

The fact that the decoder works in terms of offsets from a state base
address is also not ideal, as dynamic state base address and surface
state base address differ for iris.  However, because dynamic state
addresses start from the top of a 4GB region, and binding tables start
from addresses [0, 64K), it's highly unlikely that we'll get overlap.

We can always improve this, but for now it's better than what we had.
2019-05-23 08:07:08 -07:00
Eric Engestrom 00cfeacf31 vk/util: drop no-op compiler warning workaround
`-Wswitch` applies to `switch()`, not `case:`, and is bypassed by the
presence of a `default:` anyway, so let's drop the `default:` and move
the warning suppression to where it can make a difference, and then it
turns out that we don't need to keep a list of special cases anymore :)

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-23 15:06:11 +00:00
Erik Faye-Lund 90e7ce5bde mesa/main: make the CONSERVATIVE_RASTERIZATION_INTEL checks consistent
INTEL_conservative_rasterization isn't exposed on compatibility
contexts, nor for GLES 3.0 and below. We already do this correctly for
gl{Enable,Disable}, but we should do the same for glIsEnabled as well.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-05-23 11:43:18 +02:00