Commit Graph

98174 Commits

Author SHA1 Message Date
Eric Engestrom 13a7a2d455 amd: remove always-true BRAHMA_BUILD define
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-12-01 13:49:42 +00:00
Vadym Shovkoplias d555929239 glx/dri3: Remove unused deviceName variable
deviceName string is declared, assigned and freed but actually
never used in dri3_create_screen() function.

Fixes: 2d94601582 ("Add DRI3+Present loader")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-12-01 13:49:42 +00:00
George Kyriazis 95adbe1a4e swr/scons: Fix intermittent build failure
gen_rasterizer*.cpp depends on gen_ar_eventhandler.hpp.
Account for new dependency.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-12-01 07:47:13 -06:00
Samuel Pitoiset 80e6e71b82 radv: only reset command buffers when the allocation fails
"vkAllocateCommandBuffers can be used to create multiple command
    buffers. If the creation of any of those command buffers fails, the
    implementation must destroy all successfully created command buffer
    objects from this command, set all entries of the pCommandBuffers
    array to NULL and return the error."

This has been suggested by gabriel@system.is.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-01 11:38:34 +01:00
Samuel Pitoiset 921986b580 radv: do not dump meta shaders with RADV_DEBUG=shaders
It's really annoying and this pollutes the output especially
when a bunch of non-meta shaders are compiled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-12-01 11:38:26 +01:00
Dave Airlie 4e7f6437b5 r600: add ARB_shader_storage_buffer_object support (v3)
This just builds on the image support. Evergreen only has ssbo
for fragment and compute no other stages.

v2: handle images and ssbo in the same shader properly (Ilia)
v3: fix RESQ on buffers,
    fix missing atom emit
    fix first element offset
    use R32 format
    write separate buffer rat store path.
(from running deqp gles3.1 tests)

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 06:12:31 +00:00
Dave Airlie c758fd05d8 r600/cayman: looks like cmpxchg moved to Z
On cayman it appears the cmp component is now in Z.

Fixes:
arb_shader_image_load_store-dead-fragments on cayman.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 03:59:17 +00:00
Dave Airlie 4f3e73516c r600/shader: fix 64->32 conversions
These didn't handle the TGSI at all properly, this fixes
them to use the common path for 64->32 then adds the 32->int
on at the end.

Fixes:
generated_tests/spec/arb_gpu_shader_fp64/execution/conversion/*

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-12-01 03:48:35 +00:00
Samuel Pitoiset ff0f17da14 radv: do not allocate CMASK or DCC for small surfaces
The idea is ported from RadeonSI, but using 512x512 instead of
256x256 seems slightly better. This improves dota2 performance
by +2%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-11-30 21:38:30 +01:00
Samuel Pitoiset f5955c6bf8 radv: do not set DISABLE_LSB_CEIL on GFX9
The state no longer exists on GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-11-30 21:38:01 +01:00
Samuel Pitoiset 319f56e675 radv: remove set but unnecessary radv_color_buffer_info::micro_tile_mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-11-30 21:38:00 +01:00
Samuel Pitoiset 4eab78b03c radv: do not store gfx9_epitch in radv_color_buffer_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-11-30 21:37:58 +01:00
Dylan Baker 7776dc32eb meson: fix glxext.h install
Another typo, the glext.h header was being install instead.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 10:00:49 -08:00
Dylan Baker a80a3e4cbb meson: fix GLES3/gl31.h install
This is a typo, gl32.h is installed twice.

Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 10:00:49 -08:00
Marek Olšák 186adc514b ac/surface: always compute DCC info when DCC is possible on GFX9
The same code for VI doesn't check for scanout either.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-30 18:46:11 +01:00
Marek Olšák ed4780383c radeonsi/gfx9: fix importing shared textures with DCC
VI has 11 dwords at least. GFX9 has 10 dwords.

Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-30 18:46:11 +01:00
Jon Turney 6f0ce2617e meson: fix deps and underlinkage of libGL
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Jon Turney 5ef75cb02b meson: build src/glx/windows
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Jon Turney 3ae998a743 meson: don't require dri2proto for darwin or windows
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Jon Turney dbe36e3b17 meson: set _GNU_SOURCE on cygwin
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Jon Turney 9cdd41b18a meson: set windows glx defines
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Dylan Baker bb5d663b39 meson: fix generated source inclusion on macOS and Windows
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 15:09:21 +00:00
Vadym Shovkoplias cdb3eb7174 intel/blorp: Fix possible NULL pointer dereferencing
Fix incomplete check of input params in blorp_surf_convert_to_uncompressed()
which can lead to NULL pointer dereferencing.

Fixes: 5ae8043fed ("intel/blorp: Add an entrypoint for doing
bit-for-bit copies")
Fixes: f395d0abc8 ("intel/blorp: Internally expose
surf_convert_to_uncompressed")
Reviewed-by: Emil Velikov <emli.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
2017-11-30 16:20:05 +02:00
Tapani Pälli faccbaf3fa mesa: add AllowGLSLCrossStageInterpolationMismatch workaround
This fixes issues seen with certain versions of Unreal Engine 4 editor
and games built with that using GLSL 4.30.

v2: add driinfo_gallium change (Emil Velikov)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801
Acked-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-30 11:43:10 +02:00
Vinson Lee 8c1e4b1afc anv: Check if memfd_create is already defined.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103909
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-30 01:36:46 -08:00
Iago Toral Quiroga 8620f7ebbc i965/vec4: use a temp register to compute offsets for pull loads
64-bit pull loads are implemented by emitting 2 separate
32-bit pull load messages, where the second message loads from
an offset at +16B.

That addition of 16B to the original offset should not alter the
original offset register used as source for the pull load instruction
though, since the compiler might use that same offset register in other
instructions (for example, for other pull loads in the shader code
that take that same offset as reference).

If the pull load is 32-bit then we only need to emit one message and
we don't need to do offset calculations, but in that case the optimizer
should be able to drop the redundant MOV.

Fixes the following test on Haswell:
KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components

Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103007
2017-11-30 07:57:53 +01:00
Wladimir J. van der Laan f1a9a724f9 etnaviv: GC7000: Factor out state based texture functionality
Prepare for two texture handling paths, the descriptor-based
path will be added in a future commit. These are structured
so that the texture implementation handles its own state
emission.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:20 +01:00
Wladimir J. van der Laan 075f8cd7de etnaviv: GC7000: Move active_samplers_bits to texture
This needs to be shared between texture_plain and texture_desc.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:16 +01:00
Wladimir J. van der Laan 260a5e2a1a etnaviv: GC7000: Factor out incompatible texture handling logic
This will be shared with the texture descriptor path.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:11 +01:00
Wladimir J. van der Laan 9d1f8805b0 etnaviv: GC7000: Track dirty sampler views
Need this to efficiently emit texture descriptor invalidations.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:07 +01:00
Wladimir J. van der Laan 5cc36f9f21 etnaviv: GC7000: Make point sprites work on HALTI5
Track varying component offset of the point size output, as well as
provide the offset of the point coord input.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:33:02 +01:00
Wladimir J. van der Laan 3d09bb390a etnaviv: GC7000: State changes for HALTI3..5
Update state objects to add new state, and emit function to emit new
state.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:32:33 +01:00
Wladimir J. van der Laan acd3dff463 etnaviv: GC7000: Update screen specs for HALTI5
- This core must load shaders from memory (AFAIK)
- Yet another new location for UNIFORMS

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:32:21 +01:00
Wladimir J. van der Laan c6033e84bb etnaviv: GC7000: Update context reset for ..HALTI5
Update context reset for HALTI3..HALTI5, sorting states for the HALTI
version that has them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:28:09 +01:00
Wladimir J. van der Laan baff59ebf0 etnaviv: GC7000: No RS align when using BLT
RS align is not necessary and might even be harmful when using the BLT
engine for blitting.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:28:02 +01:00
Wladimir J. van der Laan dd3a04c2c3 etnaviv: GC7000: BLT engine blitting support
Add an implemenation of key clear_blit functions using the BLT engine
that replaced the RS on GC7000.

Also set level->size correctly for imported resources. This is important
for the BLT resolve-in-place path to work for them.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:57 +01:00
Wladimir J. van der Laan 079bbaec0c etnaviv: GC7000: Factor out RS blit functionality
Prepare for BLT-based blitting path by moving RS-based
blitting to the RS implementation file, making this
self-contained.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:53 +01:00
Wladimir J. van der Laan 77768b1859 etnaviv: GC7000: Move etna_coalesce to emit header file
Want to be able to emit state from the texture implementation,
and the blitter implementation.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:48 +01:00
Wladimir J. van der Laan 571d980695 etnaviv: GC7000: Support BLT as recipient for etna_stall
When the BLT is involved as source or target, add an extra BLT
enable/disable sequence around the sync sequence.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:27:43 +01:00
Wladimir J. van der Laan 150d8766ea etnaviv: Use only DRAW_INSTANCED on GC3000+
The blob does this, as DRAW_INSTANCED can replace fully all the other
draw commands. It is also required to handle integer vertex formats.
The other path is only there for compatibility and might go away (or at
least rot to become buggy due to dis-use) in newer hardware.

As a by-effect this changes the behavior for GC3000-, by no longer using
the index offset for DRAW_INDEXED but instead adding it to INDEX_ADDR.
This should make no difference.

Preparation for GC7000 support.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-11-30 07:26:55 +01:00
Wladimir J. van der Laan 23630ab1b6 etnaviv: Emit SCALE for vertex attributes
This is used by HALTI2+ (GC3000+) when drawing with DRAW_INSTANCED.

It is also necessary when switching between integer and floating point
vertex element formats.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-11-30 07:26:46 +01:00
Kenneth Graunke 74e38739ca i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.
We're about to add more of them, and need to pass the whole lot of them
around together when growing them.  Putting them in a struct makes this
much easier.

brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things
labeled 'batch' and 'state' now that we have multiple buffers.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke ca43616586 i965: Don't grow batch/state buffer on every emit after an overflow.
Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we
try and flush.  If we're not allowed to flush, we resort to growing the
buffer so that there's space for the data we need to emit.

We accidentally got the threshold wrong.  The first non-wrappable call
beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ),
The next call would see we were beyond STATE_SZ and think we needed to
grow a second time - when the buffer was already large enough.

We still want to flush when we hit STATE_SZ, but for growing, we should
use the actual size of the buffer as the threshold.  This way, we only
grow when actually necessary.

v2: Simplify the control flow (suggested by Jordan)

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke 52d32917e1 i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.
The original state buffer was marked with EXEC_OBJECT_CAPTURE.  When
growing it, we want to preserve that flag so we continue to capture it
in GPU hang reports.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-11-29 17:30:35 -08:00
Kenneth Graunke 2af7085460 i965: Use old_bo->align when growing batch/state buffer instead of 4096.
The intention here is make the new BO use the same alignment as the old
BO.  This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.

The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-11-29 17:30:35 -08:00
Dave Airlie 2c4861e453 r600: no need to reinit compute regs
Compute setup gets emitted into the normal gfx state buffer,
so no need to reinit the basics.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:53:22 +10:00
Dave Airlie ea355e29f7 r600: split cb setup code out from evergreen compute path.
This just makes it easier to bypass for TGSI later.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:39:25 +10:00
Dave Airlie 77c70e5fe5 r600: add support for compute pkt flags to debug dumping.
This just lets us see packets marked for compute.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:32:31 +10:00
Dave Airlie 779306c8b6 r600: fix bfe where src/dst are same.
This fixes overlaps where src/dst are the same.

Fixes a bunch of the deqp bitfield tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-30 09:32:31 +10:00
Adam Jackson 0d044351b7 gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control
Reviewed-and-tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
2017-11-29 16:00:24 -05:00