Commit Graph

45988 Commits

Author SHA1 Message Date
Lauri Kasanen e453289a77 pp: Color filters
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:05 -06:00
Lauri Kasanen e86e4cf128 pp: Docs
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:51:05 -06:00
Lauri Kasanen d2fdc58fe7 aux/Makefile,SConscript: Build PP
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:50:46 -06:00
Lauri Kasanen 421235d42a st/dri: Bind the post-processing queue to dri
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:49:33 -06:00
Lauri Kasanen 6a6441fc03 driconf: Add the PP descriptions
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-08-19 16:47:23 -06:00
Marek Olšák db71537f01 r600g: don't allocate separate depth and stencil for transfer textures on EG
The state tracker expects depth and stencil pixels interleaved.
Evergreen can bind an interleaved depth-stencil resource as a colorbuffer,
but not as a zbuffer.

The hardware can do the interleaving for us when decompressing.
2011-08-19 23:12:15 +02:00
Marek Olšák 754ea4ea76 r600g: finally enable float depth buffers on evergreen 2011-08-19 23:12:11 +02:00
Marek Olšák 565f39bdb2 r600g: rename resource -> view in create_sampler_view
The sampler view is not a resource.
Also remove the unused desc variable.
2011-08-19 23:12:11 +02:00
Marek Olšák 751a6ed893 r600g: hack around a problem with texture alignment 2011-08-19 23:12:11 +02:00
Marek Olšák 98a87a594b r600g: simplify the conditionals determining array mode 2011-08-19 23:12:11 +02:00
Marek Olšák 7f29824fd5 r600g: put depth and stencil into one backing buffer
For DRI2 sharing.
2011-08-19 23:12:11 +02:00
Marek Olšák 68c54abb2c r600g: fix depth-stencil on evergreen
Such that it actually works in apps which use both.

A separate buffer is allocated for stencil. The only exception is
the window-system-provided depth-stencil buffer, where depth and stencil
share the same buffer.

This fixes:
- fbo-depthstencil-GL_DEPTH24_STENCIL8-clear
- fbo-depthstencil-GL_DEPTH24_STENCIL8-drawpixels-FLOAT-and-USHORT
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT
2011-08-19 23:12:11 +02:00
Brian Paul 3e9dc51f82 mesa: handle array textures in GenerateMipmap(), FramebufferTexture1/2D()
This was an unfinished to-do item before.
With this patch and the two preceeding patches, piglit's
fbo-generatemipmap-array test runs and passes instead of generating
a GL error and dying on an assertion.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:11 -06:00
Brian Paul 0f8c43c34f meta: use fallback mipmap generation for 1D/2D texture arrays
We could do 1D/2D arrays with textured quad rendering, but it'll take
some work (as with 3D textures).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:11 -06:00
Brian Paul 0eb18ee557 mesa: set Q=1 for OPCODE_TEX execution
Q should not be significant for OPCODE_TEX, but it winds up getting
passed to the compute_lambda() function.  Make sure it's 1.0 to
prevent garbage values, which is effectively what we get when the
swizzle is coord.xyzz (which is what GLSL gives us).

Part of the fix for piglit's fbo-generatemipmap-array test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:10 -06:00
Brian Paul 352cab498a mesa: restructure error checking in _mesa_FramebufferTexture1D/2DEXT()
In anticipation of adding more texture targets.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-19 13:31:10 -06:00
Chad Versace f23c3ebecc mesa: Declare _mesa_meta_begin()/end() as public
Declare _mesa_meta_begin()/end() in meta.h so that drivers can write
custom meta-ops (such as HiZ resolves for i965).

This necessitates moving the the META_* macros into meta.h. To prevent
naming collisions, this commit renames each macro to be MESA_META_*.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-08-19 10:49:59 -07:00
Christoph Bumiller 778997f9df nv50: fix potential null deref in insn modifer optimization pass
Bug introduced in 34980cd153.
2011-08-19 16:57:30 +02:00
Brian Paul e975e18beb glx: use a block to fix declarations after code warning 2011-08-19 08:36:22 -06:00
Marek Olšák e330d90e91 r600g: fix a possible crash in r600_adjust_gprs 2011-08-19 14:46:25 +02:00
Brian Paul ccecc08f79 mesa: fix incorrect error code in _mesa_FramebufferTexture1D/3DEXT()
The spec says GL_INVALID_OPERATION is generated when texture!=0 and
textarget is not a legal value.  We had this right for the 2D function.
2011-08-18 11:51:53 -06:00
Paul Berry e9ae4cadf5 glapi: update .gitignore for generated ES dispatch headers
Commit 6eff33dc (glapi: generate ES dispatch headers from core mesa)
replaced the autogenerated files
src/mapi/es1api/main/{dispatch,remap_helper}.h with new autogenerated
files src/mesa/main/api_exec_es{1,2}_{dispatch,remap_helper}.h.  This
patch updates the .gitignore files to properly ignore the new
autogenerated files, and stop ignoring the old autogenerated files.

Reviewed-by: Chia-I Wu <olv@lunarg.com>
2011-08-18 10:18:22 -07:00
José Fonseca 762bf931ca llvmpipe: Don't build lp_test_arit on MSVC.
Several issues due to expf/logf/etc either not being declared,
or being defined as a macro.
2011-08-18 18:04:44 +01:00
José Fonseca a7f67b1c50 llvmpipe: snprintf->util_snprintf.
For MSVC.
2011-08-18 17:58:02 +01:00
José Fonseca 09042e08cb llvmpipe: Add u_math.h include.
Necessary on platforms with incomplete math.h
2011-08-18 16:06:00 +01:00
José Fonseca 7be4cf9c63 scons: Add support for LLVM-2.9 on Windows.
MinGW & MSVC, although I've only tested the former.
2011-08-18 16:00:59 +01:00
Kristian Høgsberg 4a7667b96b glx: Don't flush twice if we fallback to dri2CopySubBuffer
The flush extensions flush call indicates end of frame and should only
be called once per frame.  However, in the dri2SwapBuffer fallback
path, we call flush and then call dri2CopySubBuffer, which also calls
flush.  Refactor the code to only call flush once.
2011-08-18 09:46:06 -04:00
Marek Olšák 01680ce2f3 r600g: implement NV_primitive_restart functionality (v2)
Needed for GL3.

v2: evergreen support

I don't set PA_SU_SC_MODE_CNTL.MULTI_PRIM_IB_ENA.
piglit/primitive-restart does pass though. Tested on RV730 and EG-REDWOOD.
2011-08-18 00:25:07 +02:00
Marek Olšák 17867f06b1 r600g: fix scons build 2011-08-17 23:24:33 +02:00
Eric Anholt 3f78f71973 i965/fs: Fix 32-bit integer multiplication.
The MUL opcode does a 16bit * 32bit multiply, and we need to do the
MACH to get the top 16bit * 32bit added in.

Fixes fs-op-mult-int-*, fs-op-mult-ivec*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-17 11:51:01 -07:00
Christoph Bumiller 34980cd153 nv50: don't drop flags definition when merging SAT with ADD/MAD 2011-08-17 20:40:43 +02:00
Brian Paul 718b894dbb st/mesa: fix incorrect loop over instruction src regs
The array of src regs is of size 3, not 4.
2011-08-17 08:12:54 -06:00
Lauri Kasanen 65bdb878a0 st/dri: Indent driconf options 2011-08-17 00:39:17 -07:00
Lauri Kasanen 59e56957cc xmlpool.h: fix a typo 2011-08-17 00:39:17 -07:00
Lauri Kasanen b629d5ba24 xmlconfig: Make the error message more informative 2011-08-17 00:39:17 -07:00
Ian Romanick 7125f1e87d mesa: Bump instruction execution limit to 65536
Shader Model 3.0[1] requires that shaders be able to execute at least
65536 instructions.  Bump Mesa maxExec to that limit.  This allows
several vertex shaders in the OpenGL ES 2.0 conformance test suite to
run to completion.

1: http://en.wikipedia.org/wiki/High_Level_Shader_Language

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:38:44 -07:00
Ian Romanick 54c48a95e6 mesa: Add partial constant propagation pass for Mesa IR
This cleans up some code generated by the IR-to-Mesa pass for i915.
In particular, some shaders involving arrays of constant matrices
result in really bad code.

v2: Silence several warnings from merging the gl_constant_value work.
Fix DP[23] folding.  Add support for a bunch more opcodes that appear
in piglit runs on i915.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:38:39 -07:00
Ian Romanick ff2cfb8989 ir_to_mesa: Emit a MAD(b, -a, b) for !a && b
!a && b occurs frequently when nexted if-statements have been
flattened.  It should also be possible use a MAD for (a && b) || c,
though that would require a MAD_SAT.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:44 -07:00
Ian Romanick ba01df11c4 ir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGE
The operation ir_binop_all_equal is !(a.x != b.x || a.y != b.y || a.z
!= b.z || a.w != b.w).  Logical-or is implemented using addition
(followed by clampling to [0,1]) on values of 0.0 and 1.0.  Replacing
the logical-or operators with addition gives !bool((int(a.x != b.x) +
int(a.y == b.y) + int(a.z == b.z) + int(a.w == b.w)).  This can be
implemented using a dot-product with a vector of all 1.0.  After the
dot-product, the value will be an integer on the range [0,4].

Previously a SEQ instruction was used to clamp the resulting logic
value to [0,1] and invert the result.  Using an SGE instruction on the
negation of the dot-product result has the same effect.  Many older
shader architectures do not support the SEQ instruction.  It must be
emulated using two SGE instructions and a MUL.  On these
architectures, the single SGE saves two instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:43 -07:00
Ian Romanick e7bf096e8b ir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLT
The operation ir_binop_any_nequal is (a.x != b.x) || (a.y != b.y) ||
(a.z != b.z) || (a.w != b.w), and that is the same as any(bvec4(a.x !=
b.x, a.y != b.y, a.z != b.z, a.w != b.w)).  Implement the any() part
the same way the regular ir_unop_any is implemented.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:43 -07:00
Ian Romanick 92ca560d68 ir_to_mesa: Implement ir_unop_any using DP4 w/saturate or DP4 w/SLT
This is just like the ir_binop_logic_or case.  The operation
ir_unop_any is (a.x || a.y || a.z || a.w).  Logical-or is implemented
using addition (followed by clampling to [0,1]) on values of 0.0 and
1.0.  Replacing the logical-or operators with addition gives (a.x +
a.y + a.z + a.w).  This can be implemented using a dot-product with a
vector of all 1.0.

Previously a SNE instruction was used to clamp the resulting logic
value to [0,1].  In a fragment shader, using a saturate on the
dot-product has the same effect.  Adding the saturate to the
dot-product is free, so (at least) one instruction is saved.

In a vertex shader, using an SLT on the negation of the dot-product
result has the same effect.  Many older shader architectures do not
support the SNE instruction.  It must be emulated using two SLT
instructions and an ADD.  On these architectures, the single SLT saves
two instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:42 -07:00
Ian Romanick 7f4c65256c ir_to_mesa: Make ir_to_mesa_visitor::emit_dp return the instruction
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:41 -07:00
Ian Romanick 41f8ffe5e0 ir_to_mesa: Implement ir_binop_logic_or using an add w/saturate or add w/SLT
Logical-or is implemented using addition (followed by clampling to
[0,1]) on values of 0.0 and 1.0.  Replacing the logical-or operators
with addition gives a + b which has a result on the range [0, 2].

Previously a SNE instruction was used to clamp the resulting logic
value to [0,1].  In a fragment shader, using a saturate on the add has
the same effect.  Adding the saturate to the add is free, so (at
least) one instruction is saved.

In a vertex shader, using an SLT on the negation of the add result has
the same effect.  Many older shader architectures do not support the
SNE instruction.  It must be emulated using two SLT instructions and
an ADD.  On these architectures, the single SLT saves two
instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:40 -07:00
Ian Romanick 6ad08989d7 ir_to_mesa: Implement ir_unop_logic_not using 1-x
Since our logic values are 0.0 (false) and 1.0 (true), 1.0 - x
accurately implements logical not.

Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-16 14:09:40 -07:00
Chad Versace 3c9f172fe8 mesa: Add Android to list of platforms that define fpclassify()
This is a fix for the Android build.

Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-08-16 14:03:48 -07:00
Chad Versace bd064a49f1 mesa: Fix Android build by #ifdef'ing out locale support
Bionic does not support locales. This commit #ifdef's out the locale usage
in _mesa_strtof().

Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-08-16 13:43:15 -07:00
Chad Versace eb0ff1a1c0 mesa: Remove use of fpu_control.h
Remove the inclusion of fpu_control.h from compiler.h.  Since Bionic lacks
fpu_control.h, this fixes the Android build.

Also remove the sole use of the fpu_control bits, which was in debug.c.
Those were brianp's debug bits, and he approved of their removal.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
2011-08-16 13:34:33 -07:00
Eric Anholt 0ddf0f1c34 i965/vs: Fix multiplies to actually do 32-bit multiplies.
Fixes vs-op-mult-int-int and friends.
2011-08-16 13:04:43 -07:00
Eric Anholt 7bf70c29ad i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.
This was quietly occurring in some emit code I produced, and failed.
2011-08-16 13:04:43 -07:00
Eric Anholt e9a86ae337 i965/vs: Fix memory leak of ralloc context for the visitor. 2011-08-16 13:04:43 -07:00