These will be used to implement the ir3-specific shader preamble
lowering in NIR. shps is conceptually similar to getone (although it
technically can't be duplicated) and shpe is similar to other barriers,
since it has to happen after any stores to the constant file in the
preamble. Add NIR intrinsics and plumbs them through ir3.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13148>
Instructions that operate on an array read the previous state of the
array, modify it, and write a new array, at least conceptually before
RA. Previously the same register specified the previous state and acted
as the new state, but this meant that it was both a source and
destination which meant that it was getting in the way of splitting up
sources and destinations. Break out the source into a separate register,
and use the new tied-src infrastructure to share code with a6xx atomics.
With this, there are basically no more special cases for arrays in RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
Previously this was hard-coded for a6xx atomic instructions. However
we'll need a way for array destinations to point to the source with the
previous value of the array when we split them up. This is conceptually
the same as tied source/destinations for a6xx atomics, except that array
writes sometimes won't have a previous value to point to. So move this
into the IR so that it can be more dynamic. As a bonus we can move the
knowledge of a6xx atomics out of RA, where it's out-of-place, and into
the a6xx-specific code that creates them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
This means you can get dumps on android, and output on Linux goes to
stderr. However, this does mean that on Linux the output goes from
looking like:
AFTER: ir3_legalize:
block3276208368 {
0000:0001:002: cov.u32s16 hr2.x, c2.x
0000:0002:002: mov.u32u32 r0.x, c0.x
[...]
to:
MESA: info: AFTER: ir3_legalize:
MESA: info: block3405271904 {
MESA: info: 0000:0001:002: cov.u32s16 hr2.x, c2.x
MESA: info: 0000:0002:002: mov.u32u32 r0.x, c0.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Normally something with IR3_REG_ARRAY doesn't have a register assigned,
but we keep IR3_REG_ARRAY for parallel copies after RA because we need
to know the appropriate size. We want to see the register assigned for
these when printing the RA result before parallel copies are lowered.
The register is in ->array.base in this case, so initialize it to
INVALID_REG and print ->array.base if it's been assigned to something,
similar to ->num in the normal case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11422>
In particular, make sure they have a physreg assigned. This was the last
place after RA where SSA registers were created, which won't work with
the new post-RA delay calculation that relies on the physreg.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
To simplify the pre-RA merge set code and express the result live-range
splitting in RA, we need to add support for parallel copy instructions,
and for the merge set code these parallel copies need to be in SSA form.
Parallel copies have multiple destinations by necessity, but there was
no way to express this in the existing IR. In particular there was no
support for marking a register as being a destination, and no support
for indicating which destination register out of several an SSA source
refers to. This replaces ir3_register::instr with ir3_register::def and
re-purposes ir3_register::instr. I haven't propagated this into common
helpers, like ssa(), because that would vastly increase the amount of
churn and the number of places that produce such instructions should be
limited -- only RA will create parallel copies and they will be
destroyed right after RA. In the future swz will have multiple
destinations too, but it will only be created after RA via parallel copy
lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Instead of using a separate outputs array, make the "end" instruction
(or chmask) take the outputs as sources. This works better for the new
RA, because it better models the fact that outputs are consumed all at
the same time. With the old model, each output collect would be assumed
dead after it was processed and subsequent collects could use it when
inserting shuffle code, which wouldn't work, and the new RA also deletes
collect instructions after lowering them to moves so the information
would be gone after RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
We need a stable order in order to create phi instructions. In the
future we can make this more sophisticated in order to make manipulating
the CFG easier, but for now that only happens after RA, so we won't have
to worry about it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
Update the IR and packer to handle the additional cat0 fields, in
prep for adding support in the assembler (in prep for adding round
trip parsing/packing test coverage).
We don't actually use these yet from the ir3 compiler, but at least
this is one less thing to worry about when we start trying to use
them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Merge the extra tracking that is useful for generating stats from asm
(as opposed to ir), and for guestimating things like inputs and outputs
(mostly useful for r/e) into ir3's version and drop cffdec's version.
There is a small change in disasm output for the decode tools, in that
it no longer prints the used consts, but rather just the max accessed
const. This is the more useful piece of information, and avoids making
the shared regmask type big enough to deal with the const reg file.
Additional error checking for invalid regids causes crashdec to bail
out sooner when decoding memory that *might* hold valid instructions.
Also, crashdec no longer prints stats, because stats aren't very useful
when trying to decode random instruction memory (which might or might
not be valid instructions).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>
With this I also brought in a few new control flow instruction disasm
tests that I'd made back when I wrote the disasm test, but which were too
far from correct to include until now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
I had missed that LDC actually uses vec4 units for its offset. This
means that we have to create a new instruction, and lower it in
ir3_nir_lower_io_offsets, similar to the existing SSBO instructions.
Unfortunately we can't assume that loads are always vec4-aligned, so we
have to use the alignment information that NIR gives us. Unfortunately,
it's currently woefully inadequate, and will have to be fixed to give us
good codegen in the future.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4568>
Do a better job of pruning when removing unused instructions, including
cleaning up dangling false-deps.
This introduces a new ssa src pointer iterator, which makes it easy to
clear links without having to think about whether it is a normal ssa
src or a false-dep.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>
This way we can also use ir3_print from computerator, which mostly
bypasses the ir3_block construct (since it doesn't need to do
scheduling, etc)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3926>
Add some infrastructure to trace scheduler decisions. The next patch
will add some more traces, just splitting this out to reduce clutter.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Connor Abbott
Rob Clark
Emma Anholt
Eric Anholt