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freedreno/ir3+isa: Cleanup bindless cat5 samp/tex encoding 

Don't let the way they are encoded at the isa level leak thru to the
ir3 level.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>
This commit is contained in:
Rob Clark 2021-10-12 10:57:24 -07:00 committed by Marge Bot
parent d43f89f17a
commit 9516d8ce98
4 changed files with 7 additions and 21 deletions
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9
src/freedreno/ir3/ir3_compiler_nir.c
View File

@ -1117,7 +1117,7 @@ struct tex_src_info {
/* For prefetch */
unsigned tex_base, samp_base, tex_idx, samp_idx;
/* For normal tex instructions */
unsigned base, combined_idx, a1_val, flags;
unsigned base, a1_val, flags;
struct ir3_instruction *samp_tex;
};
@ -1150,11 +1150,9 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
if (info.tex_idx < 16) {
/* Everything fits within the instruction */
info.base = info.tex_base;
info.combined_idx = info.samp_idx | (info.tex_idx << 4);
} else {
info.base = info.tex_base;
info.a1_val = info.tex_idx << 3;
info.combined_idx = 0;
info.flags |= IR3_INSTR_A1EN;
}
info.samp_tex = NULL;
@ -1200,7 +1198,8 @@ emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
}
if (info.flags & IR3_INSTR_B) {
sam->cat5.tex_base = info.base;
sam->cat5.samp = info.combined_idx;
sam->cat5.samp = info.samp_idx;
sam->cat5.tex = info.tex_idx;
}
return sam;
}
@ -2305,11 +2304,9 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
info.tex_base == info.samp_base)) {
/* Everything fits within the instruction */
info.base = info.tex_base;
info.combined_idx = info.samp_idx | (info.tex_idx << 4);
} else {
info.base = info.tex_base;
info.a1_val = info.tex_idx << 3 | info.samp_base;
info.combined_idx = info.samp_idx;
info.flags |= IR3_INSTR_A1EN;
}
info.samp_tex = NULL;

2
src/freedreno/ir3/ir3_parser.y
View File

@ -984,7 +984,7 @@ cat5_flags:
| cat5_flag cat5_flags
cat5_samp: T_SAMP { instr->cat5.samp = $1; }
cat5_tex: T_TEX { if (instr->flags & IR3_INSTR_B) instr->cat5.samp |= ($1 << 4); else instr->cat5.tex = $1; }
cat5_tex: T_TEX { instr->cat5.tex = $1; }
cat5_type: '(' type ')' { instr->cat5.type = $2; }
cat5_a1: src_reg { instr->flags |= IR3_INSTR_A1EN; }

10
src/freedreno/ir3/ir3_print.c
View File

@ -340,14 +340,8 @@ print_instr(struct log_stream *stream, struct ir3_instruction *instr, int lvl)
}
if (is_tex(instr) && !(instr->flags & IR3_INSTR_S2EN)) {
if (!!(instr->flags & IR3_INSTR_B)) {
if (!!(instr->flags & IR3_INSTR_A1EN)) {
mesa_log_stream_printf(stream, ", s#%d", instr->cat5.samp);
} else {
mesa_log_stream_printf(stream, ", s#%d, t#%d",
instr->cat5.samp & 0xf,
instr->cat5.samp >> 4);
}
if (!!(instr->flags & IR3_INSTR_B) && !!(instr->flags & IR3_INSTR_A1EN)) {
mesa_log_stream_printf(stream, ", s#%d", instr->cat5.samp);
} else {
mesa_log_stream_printf(stream, ", s#%d, t#%d", instr->cat5.samp,
instr->cat5.tex);

7
src/freedreno/isa/ir3-cat5.xml
View File

@ -481,12 +481,7 @@ SOFTWARE.
<display/>
<assert low="0" high="3">0000</assert>
<encode type="struct ir3_instruction *">
<!--
TODO properly decouple the encoding from ir3 IR in this
case.. the IR has no business knowing how this gets
encoded into "SRC3"..
-->
<map name="TEX">src->cat5.samp >> 4</map>
<map name="TEX">src->cat5.tex</map>
</encode>
</bitset>