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docs/isl: fix typos & formatting 

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17522>
This commit is contained in:
Eric Engestrom 2022-07-13 18:53:22 +01:00 committed by Marge Bot
parent 648731e2bd
commit 8317de8ed3
3 changed files with 6 additions and 6 deletions
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2
docs/isl/ccs.rst
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@ -52,7 +52,7 @@ concerned, is that fast-clears use only 1 bit per cache-line pair whereas color
compression uses 2 bits. compression uses 2 bits.
What is a cache-line pair? Both the X and Y tiling formats are arranged as an What is a cache-line pair? Both the X and Y tiling formats are arranged as an
8x8 grid of cache lines. (See the [chapter on tiling](#tiling) for more 8x8 grid of cache lines. (See the :doc:`chapter on tiling <tiling>` for more
details.) In either case, a cache-line pair is a pair of cache lines whose details.) In either case, a cache-line pair is a pair of cache lines whose
starting addresses differ by 512 bytes or 8 cache lines. This results in the starting addresses differ by 512 bytes or 8 cache lines. This results in the
two cache lines being vertically adjacent when the main surface is X-tiled and two cache lines being vertically adjacent when the main surface is X-tiled and

2
docs/isl/hiz.rst
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@ -23,7 +23,7 @@ with HiZ.
As stated in the PRM, this means we need a separate HiZ or stencil buffer for As stated in the PRM, this means we need a separate HiZ or stencil buffer for
each LOD. However, it's not quite as simple as that. If you ignore layered each LOD. However, it's not quite as simple as that. If you ignore layered
rendering, things are pretty straightforward: you need one HiZ surface for each rendering, things are pretty straightforward: you need one HiZ surface for each
main surface slice With layered, rendering, however, we have to be a bit more main surface slice. With layered rendering, however, we have to be a bit more
clever because we need a "real" array surface at each LOD. ISL solves this clever because we need a "real" array surface at each LOD. ISL solves this
with a special miptree layout for layered rendering with a special miptree layout for layered rendering
:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` which lays :cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` which lays

8
docs/isl/tiling.rst
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@ -320,7 +320,7 @@ are relatively expensive in hardware while interleaving bits in a well-defined
pattern is practically free. For a format that has more than one byte per pattern is practically free. For a format that has more than one byte per
element, you simply chop bits off the bottom of the pattern, hard-code them to element, you simply chop bits off the bottom of the pattern, hard-code them to
0, and adjust bit indices as needed. For a 128-bit format, for instance, the 0, and adjust bit indices as needed. For a 128-bit format, for instance, the
Y-tiled pattern becomes u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0. The Sky Lake PRM Y-tiled pattern becomes :math:`u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0`. The Sky Lake
Vol. 5 in the section "2D Surfaces" contains an expanded version of the above PRM Vol. 5 in the section "2D Surfaces" contains an expanded version of the
table (which we will not repeat here) that also includes the bit patterns for above table (which we will not repeat here) that also includes the bit patterns
the Ys and Yf tiling formats. for the Ys and Yf tiling formats.