diff --git a/docs/isl/ccs.rst b/docs/isl/ccs.rst index 974568e70b7..e3d478b2aaf 100644 --- a/docs/isl/ccs.rst +++ b/docs/isl/ccs.rst @@ -52,7 +52,7 @@ concerned, is that fast-clears use only 1 bit per cache-line pair whereas color compression uses 2 bits. What is a cache-line pair? Both the X and Y tiling formats are arranged as an -8x8 grid of cache lines. (See the [chapter on tiling](#tiling) for more +8x8 grid of cache lines. (See the :doc:`chapter on tiling ` for more details.) In either case, a cache-line pair is a pair of cache lines whose starting addresses differ by 512 bytes or 8 cache lines. This results in the two cache lines being vertically adjacent when the main surface is X-tiled and diff --git a/docs/isl/hiz.rst b/docs/isl/hiz.rst index 0d3b34aaaea..07ddbafa14b 100644 --- a/docs/isl/hiz.rst +++ b/docs/isl/hiz.rst @@ -23,7 +23,7 @@ with HiZ. As stated in the PRM, this means we need a separate HiZ or stencil buffer for each LOD. However, it's not quite as simple as that. If you ignore layered rendering, things are pretty straightforward: you need one HiZ surface for each -main surface slice With layered, rendering, however, we have to be a bit more +main surface slice. With layered rendering, however, we have to be a bit more clever because we need a "real" array surface at each LOD. ISL solves this with a special miptree layout for layered rendering :cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` which lays diff --git a/docs/isl/tiling.rst b/docs/isl/tiling.rst index 44a44b461fc..5117e162389 100644 --- a/docs/isl/tiling.rst +++ b/docs/isl/tiling.rst @@ -320,7 +320,7 @@ are relatively expensive in hardware while interleaving bits in a well-defined pattern is practically free. For a format that has more than one byte per element, you simply chop bits off the bottom of the pattern, hard-code them to 0, and adjust bit indices as needed. For a 128-bit format, for instance, the -Y-tiled pattern becomes u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0. The Sky Lake PRM -Vol. 5 in the section "2D Surfaces" contains an expanded version of the above -table (which we will not repeat here) that also includes the bit patterns for -the Ys and Yf tiling formats. +Y-tiled pattern becomes :math:`u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0`. The Sky Lake +PRM Vol. 5 in the section "2D Surfaces" contains an expanded version of the +above table (which we will not repeat here) that also includes the bit patterns +for the Ys and Yf tiling formats.