docs/isl: fix typos & formatting
Signed-off-by: Eric Engestrom <eric@igalia.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17522>
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@ -52,7 +52,7 @@ concerned, is that fast-clears use only 1 bit per cache-line pair whereas color
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compression uses 2 bits.
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What is a cache-line pair? Both the X and Y tiling formats are arranged as an
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8x8 grid of cache lines. (See the [chapter on tiling](#tiling) for more
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8x8 grid of cache lines. (See the :doc:`chapter on tiling <tiling>` for more
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details.) In either case, a cache-line pair is a pair of cache lines whose
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starting addresses differ by 512 bytes or 8 cache lines. This results in the
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two cache lines being vertically adjacent when the main surface is X-tiled and
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@ -23,7 +23,7 @@ with HiZ.
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As stated in the PRM, this means we need a separate HiZ or stencil buffer for
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each LOD. However, it's not quite as simple as that. If you ignore layered
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rendering, things are pretty straightforward: you need one HiZ surface for each
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main surface slice With layered, rendering, however, we have to be a bit more
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main surface slice. With layered rendering, however, we have to be a bit more
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clever because we need a "real" array surface at each LOD. ISL solves this
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with a special miptree layout for layered rendering
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:cpp:enumerator:`isl_dim_layout::ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ` which lays
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@ -320,7 +320,7 @@ are relatively expensive in hardware while interleaving bits in a well-defined
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pattern is practically free. For a format that has more than one byte per
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element, you simply chop bits off the bottom of the pattern, hard-code them to
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0, and adjust bit indices as needed. For a 128-bit format, for instance, the
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Y-tiled pattern becomes u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0. The Sky Lake PRM
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Vol. 5 in the section "2D Surfaces" contains an expanded version of the above
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table (which we will not repeat here) that also includes the bit patterns for
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the Ys and Yf tiling formats.
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Y-tiled pattern becomes :math:`u_2 u_1 u_0 v_4 v_3 v_2 v_1 v_0`. The Sky Lake
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PRM Vol. 5 in the section "2D Surfaces" contains an expanded version of the
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above table (which we will not repeat here) that also includes the bit patterns
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for the Ys and Yf tiling formats.
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