332 lines
11 KiB
C
332 lines
11 KiB
C
/*
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* Copyright © 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#ifndef AC_GPU_INFO_H
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#define AC_GPU_INFO_H
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#include "amd_family.h"
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define AMD_MAX_SE 8
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#define AMD_MAX_SA_PER_SE 2
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struct amdgpu_gpu_info;
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struct amd_ip_info {
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uint8_t ver_major;
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uint8_t ver_minor;
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uint8_t num_queues;
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};
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struct radeon_info {
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/* Device info. */
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const char *name;
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char lowercase_name[32];
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const char *marketing_name;
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uint32_t num_se; /* only enabled SEs */
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uint32_t num_rb; /* only enabled RBs */
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uint32_t num_cu; /* only enabled CUs */
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uint32_t max_gpu_freq_mhz; /* also known as the shader clock */
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uint32_t max_gflops;
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uint32_t l1_cache_size;
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uint32_t l2_cache_size;
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uint32_t l3_cache_size_mb;
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uint32_t num_tcc_blocks; /* also the number of memory channels */
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uint32_t memory_freq_mhz;
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uint32_t memory_freq_mhz_effective;
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uint32_t memory_bus_width;
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uint32_t memory_bandwidth_gbps;
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uint32_t clock_crystal_freq;
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struct amd_ip_info ip[AMD_NUM_IP_TYPES];
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/* Identification. */
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/* PCI info: domain:bus:dev:func */
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uint32_t pci_domain;
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uint32_t pci_bus;
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uint32_t pci_dev;
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uint32_t pci_func;
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uint32_t pci_id;
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uint32_t pci_rev_id;
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enum radeon_family family;
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enum amd_gfx_level gfx_level;
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uint32_t family_id;
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uint32_t chip_external_rev;
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/* Flags. */
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bool is_pro_graphics;
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bool has_graphics; /* false if the chip is compute-only */
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uint32_t ib_pad_dw_mask[AMD_NUM_IP_TYPES];
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bool has_clear_state;
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bool has_distributed_tess;
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bool has_dcc_constant_encode;
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bool has_rbplus; /* if RB+ registers exist */
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bool rbplus_allowed; /* if RB+ is allowed */
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bool has_load_ctx_reg_pkt;
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bool has_out_of_order_rast;
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bool has_packed_math_16bit;
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bool has_accelerated_dot_product;
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bool cpdma_prefetch_writes_memory;
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bool has_gfx9_scissor_bug;
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bool has_tc_compat_zrange_bug;
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bool has_msaa_sample_loc_bug;
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bool has_ls_vgpr_init_bug;
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bool has_zero_index_buffer_bug;
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bool has_image_load_dcc_bug;
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bool has_two_planes_iterate256_bug;
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bool has_vgt_flush_ngg_legacy_bug;
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bool has_cs_regalloc_hang_bug;
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bool has_32bit_predication;
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bool has_3d_cube_border_color_mipmap;
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bool never_stop_sq_perf_counters;
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bool has_sqtt_rb_harvest_bug;
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bool has_sqtt_auto_flush_mode_bug;
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bool never_send_perfcounter_stop;
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bool discardable_allows_big_page;
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/* Display features. */
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/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
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/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
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bool use_display_dcc_unaligned;
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/* Allocate both aligned and unaligned DCC and use the retile blit. */
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bool use_display_dcc_with_retile_blit;
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/* Memory info. */
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uint32_t pte_fragment_size;
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uint32_t gart_page_size;
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uint32_t gart_size_kb;
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uint32_t vram_size_kb;
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uint64_t vram_vis_size_kb;
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uint32_t vram_type;
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uint32_t max_heap_size_kb;
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uint32_t min_alloc_size;
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uint32_t address32_hi;
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bool has_dedicated_vram;
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bool all_vram_visible;
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bool smart_access_memory;
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bool has_l2_uncached;
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bool r600_has_virtual_memory;
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uint32_t max_tcc_blocks;
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uint32_t tcc_cache_line_size;
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bool tcc_rb_non_coherent; /* whether L2 inv is needed for render->texture transitions */
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unsigned pc_lines;
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uint32_t lds_size_per_workgroup;
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uint32_t lds_alloc_granularity;
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uint32_t lds_encode_granularity;
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/* CP info. */
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bool gfx_ib_pad_with_type2;
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unsigned ib_alignment; /* both start and size alignment */
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uint32_t me_fw_version;
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uint32_t me_fw_feature;
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uint32_t mec_fw_version;
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uint32_t mec_fw_feature;
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uint32_t pfp_fw_version;
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uint32_t pfp_fw_feature;
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/* Multimedia info. */
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struct {
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bool uvd_decode;
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bool vcn_decode;
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bool jpeg_decode;
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bool vce_encode;
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bool uvd_encode;
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bool vcn_encode;
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} has_video_hw;
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uint32_t uvd_fw_version;
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uint32_t vce_fw_version;
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uint32_t vce_harvest_config;
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struct video_caps_info {
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struct {
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uint32_t valid;
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uint32_t max_width;
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uint32_t max_height;
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uint32_t max_pixels_per_frame;
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uint32_t max_level;
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uint32_t pad;
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} codec_info[8]; /* the number of available codecs */
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} dec_caps, enc_caps;
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/* Kernel & winsys capabilities. */
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uint32_t drm_major; /* version */
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uint32_t drm_minor;
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uint32_t drm_patchlevel;
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bool is_amdgpu;
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bool has_userptr;
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bool has_syncobj;
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bool has_timeline_syncobj;
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bool has_fence_to_handle;
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bool has_local_buffers;
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bool kernel_flushes_hdp_before_ib;
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bool htile_cmask_support_1d_tiling;
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bool si_TA_CS_BC_BASE_ADDR_allowed;
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bool has_bo_metadata;
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bool has_gpu_reset_status_query;
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bool has_eqaa_surface_allocator;
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bool has_format_bc1_through_bc7;
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bool kernel_flushes_tc_l2_after_ib;
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bool has_indirect_compute_dispatch;
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bool has_unaligned_shader_loads;
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bool has_sparse_vm_mappings;
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bool has_2d_tiling;
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bool has_read_registers_query;
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bool has_scheduled_fence_dependency;
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bool has_stable_pstate;
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/* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
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bool mid_command_buffer_preemption_enabled;
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bool has_tmz_support;
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bool kernel_has_modifiers;
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/* Shader cores. */
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uint32_t cu_mask[AMD_MAX_SE][AMD_MAX_SA_PER_SE];
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uint32_t r600_max_quad_pipes; /* wave size / 16 */
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uint32_t max_good_cu_per_sa;
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uint32_t min_good_cu_per_sa; /* min != max if SAs have different # of CUs */
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uint32_t max_se; /* number of shader engines incl. disabled ones */
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uint32_t max_sa_per_se; /* shader arrays per shader engine */
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uint32_t max_wave64_per_simd;
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uint32_t num_physical_sgprs_per_simd;
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uint32_t num_physical_wave64_vgprs_per_simd;
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uint32_t num_simd_per_compute_unit;
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uint32_t min_sgpr_alloc;
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uint32_t max_sgpr_alloc;
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uint32_t sgpr_alloc_granularity;
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uint32_t min_wave64_vgpr_alloc;
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uint32_t max_vgpr_alloc;
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uint32_t wave64_vgpr_alloc_granularity;
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uint32_t max_scratch_waves;
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/* Render backends (color + depth blocks). */
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uint32_t r300_num_gb_pipes;
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uint32_t r300_num_z_pipes;
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uint32_t r600_gb_backend_map; /* R600 harvest config */
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bool r600_gb_backend_map_valid;
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uint32_t r600_num_banks;
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uint32_t mc_arb_ramcfg;
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uint32_t gb_addr_config;
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uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
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uint32_t max_render_backends; /* number of render backends incl. disabled ones */
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uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
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uint32_t pipe_interleave_bytes;
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uint32_t enabled_rb_mask; /* GCN harvest config */
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uint64_t max_alignment; /* from addrlib */
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uint32_t pbb_max_alloc_count;
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/* Tile modes. */
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uint32_t si_tile_mode_array[32];
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uint32_t cik_macrotile_mode_array[16];
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/* AMD_CU_MASK environment variable or ~0. */
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bool spi_cu_en_has_effect;
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uint32_t spi_cu_en;
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};
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bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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struct amdgpu_gpu_info *amdinfo);
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void ac_compute_driver_uuid(char *uuid, size_t size);
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void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
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void ac_print_gpu_info(struct radeon_info *info, FILE *f);
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int ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family);
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void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p,
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uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p);
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void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config,
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unsigned *cik_raster_config_1_p, unsigned *raster_config_se);
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unsigned ac_get_compute_resource_limits(const struct radeon_info *info,
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unsigned waves_per_threadgroup, unsigned max_waves_per_sh,
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unsigned threadgroups_per_cu);
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struct ac_hs_info {
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uint32_t tess_offchip_block_dw_size;
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uint32_t max_offchip_buffers;
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uint32_t hs_offchip_param;
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uint32_t tess_factor_ring_size;
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uint32_t tess_offchip_ring_offset;
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uint32_t tess_offchip_ring_size;
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};
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void ac_get_hs_info(struct radeon_info *info,
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struct ac_hs_info *hs);
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/* Task rings BO layout information.
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* This BO is shared between GFX and ACE queues so that the ACE and GFX
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* firmware can cooperate on task->mesh dispatches and is also used to
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* store the task payload which is passed to mesh shaders.
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*
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* The driver only needs to create this BO once,
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* and it will always be able to accomodate the maximum needed
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* task payload size.
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*
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* The following memory layout is used:
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* 1. Control buffer: 9 DWORDs, 256 byte aligned
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* Used by the firmware to maintain the current state.
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* (padding)
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* 2. Draw ring: 4 DWORDs per entry, 256 byte aligned
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* Task shaders store the mesh dispatch size here.
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* (padding)
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* 3. Payload ring: 16K bytes per entry, 256 byte aligned.
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* This is where task payload is stored by task shaders and
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* read by mesh shaders.
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*
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*/
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struct ac_task_info {
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uint32_t draw_ring_offset;
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uint32_t payload_ring_offset;
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uint32_t bo_size_bytes;
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uint16_t num_entries;
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};
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/* Size of each payload entry in the task payload ring.
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* Spec requires minimum 16K bytes.
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*/
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#define AC_TASK_PAYLOAD_ENTRY_BYTES 16384
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/* Size of each draw entry in the task draw ring.
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* 4 DWORDs per entry.
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*/
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#define AC_TASK_DRAW_ENTRY_BYTES 16
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/* Size of the task control buffer. 9 DWORDs. */
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#define AC_TASK_CTRLBUF_BYTES 36
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void ac_get_task_info(struct radeon_info *info,
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struct ac_task_info *task_info);
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC_GPU_INFO_H */
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