pan/bi: Flesh out ATEST in IR

ATEST actually takes two sources and has a destination. Although the
details are a little funny, we should still model this correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
This commit is contained in:
Alyssa Rosenzweig 2020-03-18 23:02:12 -04:00 committed by Marge Bot
parent 61260819ba
commit b18d0ef708
2 changed files with 17 additions and 2 deletions

View File

@ -28,7 +28,7 @@
unsigned bi_class_props[BI_NUM_CLASSES] = {
[BI_ADD] = BI_GENERIC | BI_MODS | BI_SCHED_ALL,
[BI_ATEST] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR,
[BI_ATEST] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
[BI_BRANCH] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD,
[BI_CMP] = BI_GENERIC | BI_MODS | BI_SCHED_ALL,
[BI_BLEND] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR,

View File

@ -120,7 +120,22 @@ bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
{
if (!ctx->emitted_atest) {
bi_instruction ins = {
.type = BI_ATEST
.type = BI_ATEST,
.src = {
BIR_INDEX_REGISTER | 60 /* TODO: RA */,
bir_src_index(&instr->src[0])
},
.src_types = {
nir_type_uint32,
nir_type_float32
},
.swizzle = {
{ 0 },
{ 3, 0 } /* swizzle out the alpha */
},
.dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
.dest_type = nir_type_uint32,
.writemask = 0xF
};
bi_emit(ctx, ins);