2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Dave Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "nir/nir_builder.h"
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#include "sid.h"
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#include "vk_format.h"
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static nir_shader *
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build_resolve_compute_shader(struct radv_device *dev, bool is_integer, int samples)
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{
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nir_builder b;
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char name[64];
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nir_if *outer_if = NULL;
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
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false,
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false,
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GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
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false,
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false,
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GLSL_TYPE_FLOAT);
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snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : "float");
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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2016-10-13 01:41:23 +01:00
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b.shader->info->name = ralloc_strdup(b.shader, name);
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b.shader->info->cs.local_size[0] = 16;
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b.shader->info->cs.local_size[1] = 16;
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b.shader->info->cs.local_size[2] = 1;
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2016-10-07 00:16:09 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
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img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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2016-10-13 01:41:23 +01:00
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b.shader->info->cs.local_size[0],
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b.shader->info->cs.local_size[1],
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b.shader->info->cs.local_size[2], 0);
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2016-10-07 00:16:09 +01:00
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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src_offset->num_components = 2;
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nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
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nir_builder_instr_insert(&b, &src_offset->instr);
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nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
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dst_offset->num_components = 2;
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nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
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nir_builder_instr_insert(&b, &dst_offset->instr);
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nir_ssa_def *img_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa);
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/* do a txf_ms on each sample */
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nir_ssa_def *tmp;
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2);
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(img_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->dest_type = nir_type_float;
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tex->is_array = false;
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tex->coord_components = 2;
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tex->texture = nir_deref_var_create(tex, input_img);
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tex->sampler = NULL;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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tmp = &tex->dest.ssa;
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nir_variable *color =
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nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
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if (!is_integer && samples > 1) {
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nir_tex_instr *tex_all_same = nir_tex_instr_create(b.shader, 1);
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tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_all_same->op = nir_texop_samples_identical;
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tex_all_same->src[0].src_type = nir_tex_src_coord;
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tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
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tex_all_same->dest_type = nir_type_float;
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tex_all_same->is_array = false;
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tex_all_same->coord_components = 2;
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tex_all_same->texture = nir_deref_var_create(tex_all_same, input_img);
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tex_all_same->sampler = NULL;
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nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
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nir_builder_instr_insert(&b, &tex_all_same->instr);
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nir_ssa_def *all_same = nir_ine(&b, &tex_all_same->dest.ssa, nir_imm_int(&b, 0));
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nir_if *if_stmt = nir_if_create(b.shader);
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if_stmt->condition = nir_src_for_ssa(all_same);
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nir_cf_node_insert(b.cursor, &if_stmt->cf_node);
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b.cursor = nir_after_cf_list(&if_stmt->then_list);
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for (int i = 1; i < samples; i++) {
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nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 2);
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tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_add->op = nir_texop_txf_ms;
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tex_add->src[0].src_type = nir_tex_src_coord;
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tex_add->src[0].src = nir_src_for_ssa(img_coord);
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tex_add->src[1].src_type = nir_tex_src_ms_index;
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tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex_add->dest_type = nir_type_float;
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tex_add->is_array = false;
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tex_add->coord_components = 2;
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tex_add->texture = nir_deref_var_create(tex_add, input_img);
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tex_add->sampler = NULL;
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nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex_add->instr);
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tmp = nir_fadd(&b, tmp, &tex_add->dest.ssa);
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}
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tmp = nir_fdiv(&b, tmp, nir_imm_float(&b, samples));
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nir_store_var(&b, color, tmp, 0xf);
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b.cursor = nir_after_cf_list(&if_stmt->else_list);
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outer_if = if_stmt;
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}
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nir_store_var(&b, color, &tex->dest.ssa, 0xf);
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if (outer_if)
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b.cursor = nir_after_cf_node(&outer_if->cf_node);
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nir_ssa_def *newv = nir_load_var(&b, color);
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nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
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store->src[0] = nir_src_for_ssa(coord);
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store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
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store->src[2] = nir_src_for_ssa(newv);
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store->variables[0] = nir_deref_var_create(store, output_img);
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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static VkResult
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create_layout(struct radv_device *device)
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{
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VkResult result;
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/*
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* two descriptors one for the image being sampled
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* one for the buffer being written.
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_compute.ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_compute.p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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return VK_SUCCESS;
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fail:
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return result;
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}
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static VkResult
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create_resolve_pipeline(struct radv_device *device,
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int samples,
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bool is_integer,
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VkPipeline *pipeline)
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{
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VkResult result;
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struct radv_shader_module cs = { .nir = NULL };
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cs.nir = build_resolve_compute_shader(device, is_integer, samples);
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.resolve_compute.p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info, NULL,
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pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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ralloc_free(cs.nir);
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return VK_SUCCESS;
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fail:
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ralloc_free(cs.nir);
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return result;
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}
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VkResult
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radv_device_init_meta_resolve_compute_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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VkResult res;
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memset(&device->meta_state.resolve_compute, 0, sizeof(device->meta_state.resolve_compute));
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res = create_layout(device);
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if (res != VK_SUCCESS)
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return res;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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uint32_t samples = 1 << i;
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res = create_resolve_pipeline(device, samples, false,
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&state->resolve_compute.rc[i].pipeline);
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res = create_resolve_pipeline(device, samples, true,
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&state->resolve_compute.rc[i].i_pipeline);
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}
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return res;
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}
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void
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radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].pipeline,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].i_pipeline,
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&state->alloc);
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}
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->resolve_compute.ds_layout,
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&state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->resolve_compute.p_layout,
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&state->alloc);
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}
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void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image *src_image,
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VkImageLayout src_image_layout,
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struct radv_image *dest_image,
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VkImageLayout dest_image_layout,
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uint32_t region_count,
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const VkImageResolve *regions)
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{
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struct radv_device *device = cmd_buffer->device;
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struct radv_meta_saved_compute_state saved_state;
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const uint32_t samples = src_image->samples;
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const uint32_t samples_log2 = ffs(samples) - 1;
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radv_meta_save_compute(&saved_state, cmd_buffer, 16);
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for (uint32_t r = 0; r < region_count; ++r) {
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const VkImageResolve *region = ®ions[r];
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assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
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assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
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assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
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const uint32_t src_base_layer =
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radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
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®ion->srcOffset);
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const uint32_t dest_base_layer =
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radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource,
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®ion->dstOffset);
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const struct VkExtent3D extent =
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radv_sanitize_image_extent(src_image->type, region->extent);
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const struct VkOffset3D srcOffset =
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radv_sanitize_image_offset(src_image->type, region->srcOffset);
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const struct VkOffset3D dstOffset =
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radv_sanitize_image_offset(dest_image->type, region->dstOffset);
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2017-02-19 06:33:14 +00:00
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VkImageSubresourceRange range;
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range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
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range.baseMipLevel = region->srcSubresource.mipLevel;
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range.levelCount = 1;
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range.baseArrayLayer = src_base_layer;
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range.layerCount = region->srcSubresource.layerCount;
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radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
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2016-10-07 00:16:09 +01:00
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for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
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++layer) {
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struct radv_image_view src_iview;
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VkDescriptorSet set;
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radv_image_view_init(&src_iview, cmd_buffer->device,
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&(VkImageViewCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(src_image),
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.viewType = radv_meta_get_view_type(src_image),
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.format = src_image->vk_format,
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.subresourceRange = {
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.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.baseMipLevel = region->srcSubresource.mipLevel,
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.levelCount = 1,
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.baseArrayLayer = src_base_layer + layer,
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.layerCount = 1,
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},
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},
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cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
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struct radv_image_view dest_iview;
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radv_image_view_init(&dest_iview, cmd_buffer->device,
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&(VkImageViewCreateInfo) {
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(dest_image),
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.viewType = radv_meta_get_view_type(dest_image),
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.format = dest_image->vk_format,
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.subresourceRange = {
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.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
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.baseMipLevel = region->dstSubresource.mipLevel,
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.levelCount = 1,
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.baseArrayLayer = dest_base_layer + layer,
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.layerCount = 1,
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},
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},
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cmd_buffer, VK_IMAGE_USAGE_STORAGE_BIT);
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radv_temp_descriptor_set_create(device, cmd_buffer,
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device->meta_state.resolve_compute.ds_layout,
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&set);
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radv_UpdateDescriptorSets(radv_device_to_handle(device),
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2, /* writeCount */
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(VkWriteDescriptorSet[]) {
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = set,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]) {
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{
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2016-12-10 19:10:04 +00:00
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.sampler = VK_NULL_HANDLE,
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2016-10-07 00:16:09 +01:00
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.imageView = radv_image_view_to_handle(&src_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}
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},
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = set,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]) {
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{
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2016-12-10 19:10:04 +00:00
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.sampler = VK_NULL_HANDLE,
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2016-10-07 00:16:09 +01:00
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.imageView = radv_image_view_to_handle(&dest_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}
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}
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}, 0, NULL);
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radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.resolve_compute.p_layout, 0, 1,
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&set, 0, NULL);
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VkPipeline pipeline;
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if (vk_format_is_int(src_image->vk_format))
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
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else
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
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if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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}
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unsigned push_constants[4] = {
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srcOffset.x,
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srcOffset.y,
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dstOffset.x,
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dstOffset.y,
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};
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.resolve_compute.p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
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push_constants);
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radv_unaligned_dispatch(cmd_buffer, extent.width, extent.height, 1);
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radv_temp_descriptor_set_destroy(cmd_buffer->device, set);
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}
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}
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radv_meta_restore_compute(&saved_state, cmd_buffer, 16);
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}
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