2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2017-08-30 14:12:20 +01:00
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#include "radv_debug.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_private.h"
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#include "vk_format.h"
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2017-07-15 01:08:01 +01:00
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#include "vk_util.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_radeon_winsys.h"
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#include "sid.h"
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2017-06-05 23:33:53 +01:00
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#include "gfx9d.h"
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2016-10-07 00:16:09 +01:00
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#include "util/debug.h"
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2017-07-07 06:56:57 +01:00
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#include "util/u_atomic.h"
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2016-10-07 00:16:09 +01:00
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static unsigned
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2017-08-22 03:47:09 +01:00
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radv_choose_tiling(struct radv_device *device,
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2016-10-07 00:16:09 +01:00
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const struct radv_image_create_info *create_info)
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{
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const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
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assert(pCreateInfo->samples <= 1);
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return RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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2017-08-21 05:10:21 +01:00
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if (!vk_format_is_compressed(pCreateInfo->format) &&
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2017-08-22 03:47:09 +01:00
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!vk_format_is_depth_or_stencil(pCreateInfo->format)
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&& device->physical_device->rad_info.chip_class <= VI) {
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/* this causes hangs in some VK CTS tests on GFX9. */
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2017-08-21 05:10:21 +01:00
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/* Textures with a very small height are recommended to be linear. */
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if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
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/* Only very thin and long 2D textures should benefit from
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* linear_aligned. */
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(pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
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return RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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2017-04-13 05:12:28 +01:00
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2016-10-07 00:16:09 +01:00
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/* MSAA resources must be 2D tiled. */
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if (pCreateInfo->samples > 1)
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return RADEON_SURF_MODE_2D;
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return RADEON_SURF_MODE_2D;
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}
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2018-03-21 20:30:40 +00:00
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static bool
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2018-04-06 15:07:22 +01:00
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radv_use_tc_compat_htile_for_image(struct radv_device *device,
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const VkImageCreateInfo *pCreateInfo)
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2018-03-21 20:30:40 +00:00
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{
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/* TC-compat HTILE is only available for GFX8+. */
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if (device->physical_device->rad_info.chip_class < VI)
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return false;
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if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
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return false;
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if (pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT |
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VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
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return false;
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
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return false;
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if (pCreateInfo->mipLevels > 1)
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return false;
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/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
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* tests - disable for now */
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if (pCreateInfo->samples >= 2 &&
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pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
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return false;
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2018-03-21 20:30:42 +00:00
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/* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
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* supports 32-bit. Though, it's possible to enable TC-compat for
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* 16-bit depth surfaces if no Z planes are compressed.
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*/
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if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
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pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
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pCreateInfo->format != VK_FORMAT_D16_UNORM)
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return false;
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2018-03-21 20:30:40 +00:00
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return true;
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}
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2018-03-30 15:46:14 +01:00
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static bool
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radv_use_dcc_for_image(struct radv_device *device,
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const struct radv_image_create_info *create_info,
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const VkImageCreateInfo *pCreateInfo)
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{
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bool dcc_compatible_formats;
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bool blendable;
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2018-05-10 04:40:21 +01:00
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bool shareable = vk_find_struct_const(pCreateInfo->pNext,
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EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
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2018-03-30 15:46:14 +01:00
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/* DCC (Delta Color Compression) is only available for GFX8+. */
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if (device->physical_device->rad_info.chip_class < VI)
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return false;
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if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
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return false;
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2018-05-10 04:40:21 +01:00
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/* FIXME: DCC is broken for shareable images starting with GFX9 */
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if (device->physical_device->rad_info.chip_class >= GFX9 &&
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shareable)
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return false;
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2018-03-30 15:46:14 +01:00
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/* TODO: Enable DCC for storage images. */
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if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
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(pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR))
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return false;
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
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return false;
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/* TODO: Enable DCC for mipmaps and array layers. */
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if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
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return false;
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if (create_info->scanout)
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return false;
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2018-04-25 09:56:15 +01:00
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/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
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* 2x can be enabled with an option.
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*/
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if (pCreateInfo->samples > 2 ||
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(pCreateInfo->samples == 2 &&
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!device->physical_device->dcc_msaa_allowed))
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2018-03-30 15:46:14 +01:00
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return false;
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/* Determine if the formats are DCC compatible. */
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dcc_compatible_formats =
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radv_is_colorbuffer_format_supported(pCreateInfo->format,
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&blendable);
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if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
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const struct VkImageFormatListCreateInfoKHR *format_list =
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(const struct VkImageFormatListCreateInfoKHR *)
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vk_find_struct_const(pCreateInfo->pNext,
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IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
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/* We have to ignore the existence of the list if viewFormatCount = 0 */
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if (format_list && format_list->viewFormatCount) {
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/* compatibility is transitive, so we only need to check
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* one format with everything else. */
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for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
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if (!radv_dcc_formats_compatible(pCreateInfo->format,
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format_list->pViewFormats[i]))
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dcc_compatible_formats = false;
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}
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} else {
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dcc_compatible_formats = false;
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}
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}
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if (!dcc_compatible_formats)
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return false;
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return true;
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}
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2016-10-07 00:16:09 +01:00
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static int
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radv_init_surface(struct radv_device *device,
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struct radeon_surf *surface,
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const struct radv_image_create_info *create_info)
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{
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const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
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unsigned array_mode = radv_choose_tiling(device, create_info);
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const struct vk_format_description *desc =
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vk_format_description(pCreateInfo->format);
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2018-03-30 15:46:14 +01:00
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bool is_depth, is_stencil;
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2016-10-07 00:16:09 +01:00
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is_depth = vk_format_has_depth(desc);
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is_stencil = vk_format_has_stencil(desc);
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surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
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surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
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2017-07-06 07:23:25 +01:00
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surface->bpe = vk_format_get_blocksize(vk_format_depth_only(pCreateInfo->format));
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2016-10-07 00:16:09 +01:00
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/* align byte per element on dword */
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if (surface->bpe == 3) {
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surface->bpe = 4;
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}
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surface->flags = RADEON_SURF_SET(array_mode, MODE);
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switch (pCreateInfo->imageType){
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case VK_IMAGE_TYPE_1D:
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if (pCreateInfo->arrayLayers > 1)
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
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else
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
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break;
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case VK_IMAGE_TYPE_2D:
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if (pCreateInfo->arrayLayers > 1)
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
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else
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
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break;
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case VK_IMAGE_TYPE_3D:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
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break;
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default:
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unreachable("unhandled image type");
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}
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if (is_depth) {
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surface->flags |= RADEON_SURF_ZBUFFER;
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2018-04-06 15:07:22 +01:00
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if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
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2017-05-09 07:26:07 +01:00
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surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
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2016-10-07 00:16:09 +01:00
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}
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if (is_stencil)
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2017-05-10 21:33:13 +01:00
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surface->flags |= RADEON_SURF_SBUFFER;
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2016-10-07 00:16:09 +01:00
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2017-07-17 11:14:33 +01:00
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surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
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2016-10-07 00:16:09 +01:00
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2018-03-30 15:46:14 +01:00
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if (!radv_use_dcc_for_image(device, create_info, pCreateInfo))
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2016-10-07 00:16:09 +01:00
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surface->flags |= RADEON_SURF_DISABLE_DCC;
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2018-03-30 15:46:14 +01:00
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2016-10-07 00:16:09 +01:00
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if (create_info->scanout)
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surface->flags |= RADEON_SURF_SCANOUT;
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return 0;
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}
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2017-09-22 17:21:33 +01:00
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2016-10-07 00:16:09 +01:00
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static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
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{
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2017-01-16 20:23:48 +00:00
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return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
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2016-10-07 00:16:09 +01:00
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}
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static inline unsigned
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si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
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{
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if (stencil)
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2017-05-10 22:01:00 +01:00
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return image->surface.u.legacy.stencil_tiling_index[level];
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2016-10-07 00:16:09 +01:00
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else
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2017-05-10 22:01:00 +01:00
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return image->surface.u.legacy.tiling_index[level];
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2016-10-07 00:16:09 +01:00
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}
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static unsigned radv_map_swizzle(unsigned swizzle)
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{
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switch (swizzle) {
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case VK_SWIZZLE_Y:
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return V_008F0C_SQ_SEL_Y;
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case VK_SWIZZLE_Z:
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return V_008F0C_SQ_SEL_Z;
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case VK_SWIZZLE_W:
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return V_008F0C_SQ_SEL_W;
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case VK_SWIZZLE_0:
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return V_008F0C_SQ_SEL_0;
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case VK_SWIZZLE_1:
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return V_008F0C_SQ_SEL_1;
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default: /* VK_SWIZZLE_X */
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return V_008F0C_SQ_SEL_X;
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}
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}
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static void
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radv_make_buffer_descriptor(struct radv_device *device,
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struct radv_buffer *buffer,
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VkFormat vk_format,
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unsigned offset,
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unsigned range,
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uint32_t *state)
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{
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const struct vk_format_description *desc;
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unsigned stride;
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2017-09-17 11:15:02 +01:00
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uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
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2016-10-07 00:16:09 +01:00
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uint64_t va = gpu_address + buffer->offset;
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unsigned num_format, data_format;
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int first_non_void;
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desc = vk_format_description(vk_format);
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first_non_void = vk_format_get_first_non_void_channel(vk_format);
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stride = desc->block.bits / 8;
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num_format = radv_translate_buffer_numformat(desc, first_non_void);
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data_format = radv_translate_buffer_dataformat(desc, first_non_void);
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va += offset;
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state[0] = va;
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state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(stride);
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2017-07-24 11:42:54 +01:00
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2017-08-24 02:47:14 +01:00
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if (device->physical_device->rad_info.chip_class != VI && stride) {
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2017-07-24 11:42:54 +01:00
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range /= stride;
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}
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2016-10-07 00:16:09 +01:00
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state[2] = range;
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state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
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|
|
|
S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
|
|
|
|
S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
|
|
|
|
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
|
|
|
|
S_008F0C_NUM_FORMAT(num_format) |
|
|
|
|
S_008F0C_DATA_FORMAT(data_format);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
si_set_mutable_tex_desc_fields(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
2017-05-10 22:01:00 +01:00
|
|
|
const struct legacy_surf_level *base_level_info,
|
2016-10-07 00:16:09 +01:00
|
|
|
unsigned base_level, unsigned first_level,
|
|
|
|
unsigned block_width, bool is_stencil,
|
2017-12-23 10:42:18 +00:00
|
|
|
bool is_storage_image, uint32_t *state)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2017-09-17 11:15:02 +01:00
|
|
|
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
|
2017-06-05 23:54:38 +01:00
|
|
|
uint64_t va = gpu_address;
|
|
|
|
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
|
|
|
|
uint64_t meta_va = 0;
|
|
|
|
if (chip_class >= GFX9) {
|
|
|
|
if (is_stencil)
|
|
|
|
va += image->surface.u.gfx9.stencil_offset;
|
|
|
|
else
|
|
|
|
va += image->surface.u.gfx9.surf_offset;
|
|
|
|
} else
|
|
|
|
va += base_level_info->offset;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
state[0] = va >> 8;
|
2017-08-15 03:40:41 +01:00
|
|
|
if (chip_class >= GFX9 ||
|
|
|
|
base_level_info->mode == RADEON_SURF_MODE_2D)
|
|
|
|
state[0] |= image->surface.tile_swizzle;
|
2017-06-05 23:54:38 +01:00
|
|
|
state[1] &= C_008F14_BASE_ADDRESS_HI;
|
2016-10-07 00:16:09 +01:00
|
|
|
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
|
|
|
|
|
2017-06-05 23:54:38 +01:00
|
|
|
if (chip_class >= VI) {
|
|
|
|
state[6] &= C_008F28_COMPRESSION_EN;
|
|
|
|
state[7] = 0;
|
2018-04-06 15:00:08 +01:00
|
|
|
if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
|
2017-06-12 20:54:08 +01:00
|
|
|
meta_va = gpu_address + image->dcc_offset;
|
2017-06-05 23:54:38 +01:00
|
|
|
if (chip_class <= VI)
|
|
|
|
meta_va += base_level_info->dcc_offset;
|
2018-04-06 15:17:26 +01:00
|
|
|
} else if (!is_storage_image &&
|
|
|
|
radv_image_is_tc_compat_htile(image)) {
|
2017-05-09 07:26:07 +01:00
|
|
|
meta_va = gpu_address + image->htile_offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (meta_va) {
|
2017-06-05 23:54:38 +01:00
|
|
|
state[6] |= S_008F28_COMPRESSION_EN(1);
|
|
|
|
state[7] = meta_va >> 8;
|
2017-08-15 03:40:41 +01:00
|
|
|
state[7] |= image->surface.tile_swizzle;
|
2017-06-05 23:54:38 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chip_class >= GFX9) {
|
|
|
|
state[3] &= C_008F1C_SW_MODE;
|
|
|
|
state[4] &= C_008F20_PITCH_GFX9;
|
|
|
|
|
|
|
|
if (is_stencil) {
|
|
|
|
state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
|
|
|
|
state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
|
|
|
|
} else {
|
|
|
|
state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode);
|
|
|
|
state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch);
|
|
|
|
}
|
|
|
|
|
|
|
|
state[5] &= C_008F24_META_DATA_ADDRESS &
|
|
|
|
C_008F24_META_PIPE_ALIGNED &
|
|
|
|
C_008F24_META_RB_ALIGNED;
|
|
|
|
if (meta_va) {
|
|
|
|
struct gfx9_surf_meta_flags meta;
|
|
|
|
|
|
|
|
if (image->dcc_offset)
|
|
|
|
meta = image->surface.u.gfx9.dcc;
|
|
|
|
else
|
|
|
|
meta = image->surface.u.gfx9.htile;
|
|
|
|
|
|
|
|
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
|
|
|
|
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
|
|
|
|
S_008F24_META_RB_ALIGNED(meta.rb_aligned);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* SI-CI-VI */
|
|
|
|
unsigned pitch = base_level_info->nblk_x * block_width;
|
|
|
|
unsigned index = si_tile_mode_index(image, base_level, is_stencil);
|
|
|
|
|
|
|
|
state[3] &= C_008F1C_TILING_INDEX;
|
|
|
|
state[3] |= S_008F1C_TILING_INDEX(index);
|
|
|
|
state[4] &= C_008F20_PITCH_GFX6;
|
|
|
|
state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
|
2017-08-16 06:20:29 +01:00
|
|
|
unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
|
|
|
|
return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
|
2017-08-16 06:20:29 +01:00
|
|
|
|
|
|
|
/* GFX9 allocates 1D textures as 2D. */
|
|
|
|
if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
|
|
|
|
image_type = VK_IMAGE_TYPE_2D;
|
2016-10-07 00:16:09 +01:00
|
|
|
switch (image_type) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
if (nr_samples > 1)
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
|
|
|
|
else
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
if (view_type == VK_IMAGE_VIEW_TYPE_3D)
|
|
|
|
return V_008F1C_SQ_RSRC_IMG_3D;
|
|
|
|
else
|
|
|
|
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
|
|
|
|
default:
|
2018-05-09 22:26:21 +01:00
|
|
|
unreachable("illegal image type");
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
}
|
2017-06-05 23:54:38 +01:00
|
|
|
|
2017-12-29 01:32:36 +00:00
|
|
|
static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
|
2017-06-05 23:54:38 +01:00
|
|
|
{
|
|
|
|
unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
|
|
|
|
|
|
|
|
if (swizzle[3] == VK_SWIZZLE_X) {
|
|
|
|
/* For the pre-defined border color values (white, opaque
|
|
|
|
* black, transparent black), the only thing that matters is
|
|
|
|
* that the alpha channel winds up in the correct place
|
|
|
|
* (because the RGB channels are all the same) so either of
|
|
|
|
* these enumerations will work.
|
|
|
|
*/
|
|
|
|
if (swizzle[2] == VK_SWIZZLE_Y)
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
|
|
|
|
else
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
|
|
|
|
} else if (swizzle[0] == VK_SWIZZLE_X) {
|
|
|
|
if (swizzle[1] == VK_SWIZZLE_Y)
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
|
|
|
|
else
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
|
|
|
|
} else if (swizzle[1] == VK_SWIZZLE_X) {
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
|
|
|
|
} else if (swizzle[2] == VK_SWIZZLE_X) {
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
|
|
|
|
}
|
|
|
|
|
|
|
|
return bc_swizzle;
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
/**
|
|
|
|
* Build the sampler view descriptor for a texture.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
si_make_texture_descriptor(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
2017-07-12 10:29:52 +01:00
|
|
|
bool is_storage_image,
|
2016-10-07 00:16:09 +01:00
|
|
|
VkImageViewType view_type,
|
|
|
|
VkFormat vk_format,
|
|
|
|
const VkComponentMapping *mapping,
|
|
|
|
unsigned first_level, unsigned last_level,
|
|
|
|
unsigned first_layer, unsigned last_layer,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
uint32_t *state,
|
|
|
|
uint32_t *fmask_state)
|
|
|
|
{
|
|
|
|
const struct vk_format_description *desc;
|
|
|
|
enum vk_swizzle swizzle[4];
|
|
|
|
int first_non_void;
|
|
|
|
unsigned num_format, data_format, type;
|
|
|
|
|
|
|
|
desc = vk_format_description(vk_format);
|
|
|
|
|
|
|
|
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
|
|
|
|
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
|
2016-11-15 06:46:50 +00:00
|
|
|
vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
|
2016-10-07 00:16:09 +01:00
|
|
|
} else {
|
|
|
|
vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
|
|
|
|
}
|
|
|
|
|
|
|
|
first_non_void = vk_format_get_first_non_void_channel(vk_format);
|
|
|
|
|
|
|
|
num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
|
|
|
|
if (num_format == ~0) {
|
|
|
|
num_format = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
|
|
|
|
if (data_format == ~0) {
|
|
|
|
data_format = 0;
|
|
|
|
}
|
|
|
|
|
2017-12-27 01:22:58 +00:00
|
|
|
/* S8 with either Z16 or Z32 HTILE need a special format. */
|
2017-12-07 10:39:46 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
vk_format == VK_FORMAT_S8_UINT &&
|
2018-04-06 15:17:26 +01:00
|
|
|
radv_image_is_tc_compat_htile(image)) {
|
2017-12-27 01:22:58 +00:00
|
|
|
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
|
|
|
|
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
|
|
|
|
else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
|
|
|
|
data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
|
|
|
|
}
|
2017-05-02 00:49:14 +01:00
|
|
|
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
|
2017-08-16 06:20:29 +01:00
|
|
|
is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
|
2016-10-07 00:16:09 +01:00
|
|
|
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
|
|
|
|
height = 1;
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
|
|
|
|
type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
|
|
|
|
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size / 6;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
state[0] = 0;
|
2016-10-01 00:53:05 +01:00
|
|
|
state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
|
|
|
|
S_008F14_NUM_FORMAT_GFX6(num_format));
|
2016-10-07 00:16:09 +01:00
|
|
|
state[2] = (S_008F18_WIDTH(width - 1) |
|
2017-04-28 07:17:10 +01:00
|
|
|
S_008F18_HEIGHT(height - 1) |
|
|
|
|
S_008F18_PERF_MOD(4));
|
2016-10-07 00:16:09 +01:00
|
|
|
state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
|
|
|
|
S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
|
|
|
|
S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
|
|
|
|
S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
|
2017-05-02 00:49:14 +01:00
|
|
|
S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
|
2016-10-07 00:16:09 +01:00
|
|
|
0 : first_level) |
|
2017-05-02 00:49:14 +01:00
|
|
|
S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
2016-10-07 00:16:09 +01:00
|
|
|
last_level) |
|
|
|
|
S_008F1C_TYPE(type));
|
2017-06-05 02:09:30 +01:00
|
|
|
state[4] = 0;
|
|
|
|
state[5] = S_008F24_BASE_ARRAY(first_layer);
|
2016-10-07 00:16:09 +01:00
|
|
|
state[6] = 0;
|
|
|
|
state[7] = 0;
|
|
|
|
|
2017-06-05 23:54:38 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
2017-12-29 01:32:36 +00:00
|
|
|
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
|
2017-06-05 23:54:38 +01:00
|
|
|
|
2018-05-09 22:26:21 +01:00
|
|
|
/* Depth is the last accessible layer on Gfx9.
|
2017-06-05 23:54:38 +01:00
|
|
|
* The hw doesn't need to know the total number of layers.
|
|
|
|
*/
|
|
|
|
if (type == V_008F1C_SQ_RSRC_IMG_3D)
|
|
|
|
state[4] |= S_008F20_DEPTH(depth - 1);
|
|
|
|
else
|
|
|
|
state[4] |= S_008F20_DEPTH(last_layer);
|
|
|
|
|
|
|
|
state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
|
|
|
|
state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
2017-08-21 08:27:25 +01:00
|
|
|
image->info.levels - 1);
|
2017-06-05 23:54:38 +01:00
|
|
|
} else {
|
2017-06-05 02:09:30 +01:00
|
|
|
state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
|
|
|
|
state[4] |= S_008F20_DEPTH(depth - 1);
|
|
|
|
state[5] |= S_008F24_LAST_ARRAY(last_layer);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
if (image->dcc_offset) {
|
|
|
|
unsigned swap = radv_translate_colorswap(vk_format, FALSE);
|
|
|
|
|
|
|
|
state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
|
|
|
|
} else {
|
|
|
|
/* The last dword is unused by hw. The shader uses it to clear
|
|
|
|
* bits in the first dword of sampler state.
|
|
|
|
*/
|
2017-05-02 00:49:14 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
|
2016-10-07 00:16:09 +01:00
|
|
|
if (first_level == last_level)
|
|
|
|
state[7] = C_008F30_MAX_ANISO_RATIO;
|
|
|
|
else
|
|
|
|
state[7] = 0xffffffff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize the sampler view for FMASK. */
|
2018-04-06 14:37:28 +01:00
|
|
|
if (radv_image_has_fmask(image)) {
|
2017-06-05 23:54:38 +01:00
|
|
|
uint32_t fmask_format, num_format;
|
2017-09-17 11:15:02 +01:00
|
|
|
uint64_t gpu_address = radv_buffer_get_va(image->bo);
|
2016-10-07 00:16:09 +01:00
|
|
|
uint64_t va;
|
|
|
|
|
|
|
|
va = gpu_address + image->offset + image->fmask.offset;
|
|
|
|
|
2017-06-05 23:54:38 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
|
|
|
|
switch (image->info.samples) {
|
|
|
|
case 2:
|
|
|
|
num_format = V_008F14_IMG_FMASK_8_2_2;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
num_format = V_008F14_IMG_FMASK_8_4_4;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
num_format = V_008F14_IMG_FMASK_32_8_8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("invalid nr_samples");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (image->info.samples) {
|
|
|
|
case 2:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
|
|
|
|
}
|
|
|
|
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
fmask_state[0] = va >> 8;
|
2017-08-15 03:40:41 +01:00
|
|
|
fmask_state[0] |= image->fmask.tile_swizzle;
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
|
2016-10-01 00:53:05 +01:00
|
|
|
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
|
2017-06-05 23:54:38 +01:00
|
|
|
S_008F14_NUM_FORMAT_GFX6(num_format);
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[2] = S_008F18_WIDTH(width - 1) |
|
|
|
|
S_008F18_HEIGHT(height - 1);
|
|
|
|
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
|
2018-03-19 07:13:46 +00:00
|
|
|
S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
|
2017-06-05 02:09:30 +01:00
|
|
|
fmask_state[4] = 0;
|
|
|
|
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[6] = 0;
|
|
|
|
fmask_state[7] = 0;
|
2017-06-05 02:09:30 +01:00
|
|
|
|
2017-06-05 23:54:38 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
fmask_state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.fmask.swizzle_mode);
|
|
|
|
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
|
|
|
|
S_008F20_PITCH_GFX9(image->surface.u.gfx9.fmask.epitch);
|
|
|
|
fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->surface.u.gfx9.cmask.pipe_aligned) |
|
|
|
|
S_008F24_META_RB_ALIGNED(image->surface.u.gfx9.cmask.rb_aligned);
|
|
|
|
} else {
|
2017-06-05 02:09:30 +01:00
|
|
|
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
|
|
|
|
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
|
|
|
|
S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
|
|
|
|
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
|
|
|
|
}
|
2017-06-09 02:11:29 +01:00
|
|
|
} else if (fmask_state)
|
|
|
|
memset(fmask_state, 0, 8 * 4);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_query_opaque_metadata(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radeon_bo_metadata *md)
|
|
|
|
{
|
|
|
|
static const VkComponentMapping fixedmapping;
|
|
|
|
uint32_t desc[8], i;
|
|
|
|
|
|
|
|
/* Metadata image format format version 1:
|
|
|
|
* [0] = 1 (metadata format identifier)
|
|
|
|
* [1] = (VENDOR_ID << 16) | PCI_ID
|
|
|
|
* [2:9] = image descriptor for the whole resource
|
|
|
|
* [2] is always 0, because the base address is cleared
|
|
|
|
* [9] is the DCC offset bits [39:8] from the beginning of
|
|
|
|
* the buffer
|
|
|
|
* [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
|
|
|
|
*/
|
|
|
|
md->metadata[0] = 1; /* metadata image format version 1 */
|
|
|
|
|
|
|
|
/* TILE_MODE_INDEX is ambiguous without a PCI ID. */
|
|
|
|
md->metadata[1] = si_get_bo_metadata_word1(device);
|
|
|
|
|
|
|
|
|
2017-07-12 10:29:52 +01:00
|
|
|
si_make_texture_descriptor(device, image, false,
|
2016-10-07 00:16:09 +01:00
|
|
|
(VkImageViewType)image->type, image->vk_format,
|
2017-05-02 00:49:14 +01:00
|
|
|
&fixedmapping, 0, image->info.levels - 1, 0,
|
|
|
|
image->info.array_size,
|
|
|
|
image->info.width, image->info.height,
|
|
|
|
image->info.depth,
|
2016-10-07 00:16:09 +01:00
|
|
|
desc, NULL);
|
|
|
|
|
2017-05-10 22:01:00 +01:00
|
|
|
si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
|
2017-12-23 10:42:18 +00:00
|
|
|
image->surface.blk_w, false, false, desc);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
/* Clear the base address and set the relative DCC offset. */
|
|
|
|
desc[0] = 0;
|
|
|
|
desc[1] &= C_008F14_BASE_ADDRESS_HI;
|
|
|
|
desc[7] = image->dcc_offset >> 8;
|
|
|
|
|
|
|
|
/* Dwords [2:9] contain the image descriptor. */
|
|
|
|
memcpy(&md->metadata[2], desc, sizeof(desc));
|
|
|
|
|
|
|
|
/* Dwords [10:..] contain the mipmap level offsets. */
|
2017-08-15 05:02:54 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class <= VI) {
|
|
|
|
for (i = 0; i <= image->info.levels - 1; i++)
|
|
|
|
md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
|
|
|
|
md->size_metadata = (11 + image->info.levels - 1) * 4;
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_init_metadata(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radeon_bo_metadata *metadata)
|
|
|
|
{
|
|
|
|
struct radeon_surf *surface = &image->surface;
|
|
|
|
|
|
|
|
memset(metadata, 0, sizeof(*metadata));
|
|
|
|
|
2017-05-24 02:37:06 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
|
|
|
|
} else {
|
|
|
|
metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
|
|
|
|
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
|
|
|
|
metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
|
|
|
|
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
|
|
|
|
metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
|
|
|
|
metadata->u.legacy.bankw = surface->u.legacy.bankw;
|
|
|
|
metadata->u.legacy.bankh = surface->u.legacy.bankh;
|
|
|
|
metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
|
|
|
|
metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
|
|
|
|
metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
|
|
|
|
metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
|
|
|
|
metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_query_opaque_metadata(device, image, metadata);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The number of samples can be specified independently of the texture. */
|
|
|
|
static void
|
|
|
|
radv_image_get_fmask_info(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
unsigned nr_samples,
|
|
|
|
struct radv_fmask_info *out)
|
|
|
|
{
|
2017-06-05 23:54:38 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
2018-05-01 03:35:51 +01:00
|
|
|
out->alignment = image->surface.fmask_alignment;
|
|
|
|
out->size = image->surface.fmask_size;
|
|
|
|
out->tile_swizzle = image->surface.fmask_tile_swizzle;
|
2017-06-05 23:54:38 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-05-01 01:54:06 +01:00
|
|
|
out->slice_tile_max = image->surface.u.legacy.fmask.slice_tile_max;
|
|
|
|
out->tile_mode_index = image->surface.u.legacy.fmask.tiling_index;
|
|
|
|
out->pitch_in_pixels = image->surface.u.legacy.fmask.pitch_in_pixels;
|
|
|
|
out->bank_height = image->surface.u.legacy.fmask.bankh;
|
2018-05-01 03:35:51 +01:00
|
|
|
out->tile_swizzle = image->surface.fmask_tile_swizzle;
|
|
|
|
out->alignment = image->surface.fmask_alignment;
|
|
|
|
out->size = image->surface.fmask_size;
|
2017-08-07 22:34:00 +01:00
|
|
|
|
|
|
|
assert(!out->tile_swizzle || !image->shareable);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_image_alloc_fmask(struct radv_device *device,
|
|
|
|
struct radv_image *image)
|
|
|
|
{
|
2017-05-02 00:49:14 +01:00
|
|
|
radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
image->fmask.offset = align64(image->size, image->fmask.alignment);
|
|
|
|
image->size = image->fmask.offset + image->fmask.size;
|
2017-02-07 00:31:11 +00:00
|
|
|
image->alignment = MAX2(image->alignment, image->fmask.alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_image_get_cmask_info(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radv_cmask_info *out)
|
|
|
|
{
|
2017-01-16 20:23:48 +00:00
|
|
|
unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
|
|
|
|
unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
|
2016-10-07 00:16:09 +01:00
|
|
|
unsigned cl_width, cl_height;
|
|
|
|
|
2017-06-05 23:54:38 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
2018-06-22 03:50:51 +01:00
|
|
|
out->alignment = image->surface.cmask_alignment;
|
|
|
|
out->size = image->surface.cmask_size;
|
2017-06-05 23:54:38 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
switch (num_pipes) {
|
|
|
|
case 2:
|
|
|
|
cl_width = 32;
|
|
|
|
cl_height = 16;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
cl_width = 32;
|
|
|
|
cl_height = 32;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
cl_width = 64;
|
|
|
|
cl_height = 32;
|
|
|
|
break;
|
|
|
|
case 16: /* Hawaii */
|
|
|
|
cl_width = 64;
|
|
|
|
cl_height = 64;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned base_align = num_pipes * pipe_interleave_bytes;
|
|
|
|
|
2017-05-02 00:58:33 +01:00
|
|
|
unsigned width = align(image->info.width, cl_width*8);
|
|
|
|
unsigned height = align(image->info.height, cl_height*8);
|
2016-10-07 00:16:09 +01:00
|
|
|
unsigned slice_elements = (width * height) / (8*8);
|
|
|
|
|
|
|
|
/* Each element of CMASK is a nibble. */
|
|
|
|
unsigned slice_bytes = slice_elements / 2;
|
|
|
|
|
|
|
|
out->slice_tile_max = (width * height) / (128*128);
|
|
|
|
if (out->slice_tile_max)
|
|
|
|
out->slice_tile_max -= 1;
|
|
|
|
|
|
|
|
out->alignment = MAX2(256, base_align);
|
2017-05-02 00:49:14 +01:00
|
|
|
out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
|
2016-10-07 00:16:09 +01:00
|
|
|
align(slice_bytes, base_align);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_image_alloc_cmask(struct radv_device *device,
|
|
|
|
struct radv_image *image)
|
|
|
|
{
|
2017-03-02 21:39:10 +00:00
|
|
|
uint32_t clear_value_size = 0;
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_image_get_cmask_info(device, image, &image->cmask);
|
|
|
|
|
|
|
|
image->cmask.offset = align64(image->size, image->cmask.alignment);
|
|
|
|
/* + 8 for storing the clear values */
|
2017-03-02 21:39:10 +00:00
|
|
|
if (!image->clear_value_offset) {
|
|
|
|
image->clear_value_offset = image->cmask.offset + image->cmask.size;
|
|
|
|
clear_value_size = 8;
|
|
|
|
}
|
|
|
|
image->size = image->cmask.offset + image->cmask.size + clear_value_size;
|
2017-02-06 23:24:16 +00:00
|
|
|
image->alignment = MAX2(image->alignment, image->cmask.alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2017-09-29 15:48:07 +01:00
|
|
|
radv_image_alloc_dcc(struct radv_image *image)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
|
2017-03-02 21:39:10 +00:00
|
|
|
/* + 16 for storing the clear values + dcc pred */
|
2016-10-07 00:16:09 +01:00
|
|
|
image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
|
2017-03-02 21:39:10 +00:00
|
|
|
image->dcc_pred_offset = image->clear_value_offset + 8;
|
|
|
|
image->size = image->dcc_offset + image->surface.dcc_size + 16;
|
2017-02-06 23:45:11 +00:00
|
|
|
image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2017-09-29 15:48:07 +01:00
|
|
|
radv_image_alloc_htile(struct radv_image *image)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2017-03-06 23:58:04 +00:00
|
|
|
image->htile_offset = align64(image->size, image->surface.htile_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
/* + 8 for storing the clear values */
|
2017-03-06 23:58:04 +00:00
|
|
|
image->clear_value_offset = image->htile_offset + image->surface.htile_size;
|
|
|
|
image->size = image->clear_value_offset + 8;
|
|
|
|
image->alignment = align64(image->alignment, image->surface.htile_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2017-09-29 15:48:07 +01:00
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
|
|
|
|
{
|
2017-11-29 13:48:32 +00:00
|
|
|
if (image->info.samples <= 1 &&
|
2017-12-21 16:45:23 +00:00
|
|
|
image->info.width * image->info.height <= 512 * 512) {
|
2017-11-29 13:48:32 +00:00
|
|
|
/* Do not enable CMASK or DCC for small surfaces where the cost
|
|
|
|
* of the eliminate pass can be higher than the benefit of fast
|
|
|
|
* clear. RadeonSI does this, but the image threshold is
|
|
|
|
* different.
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-09-29 15:48:07 +01:00
|
|
|
return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
|
|
|
|
(image->exclusive || image->queue_family_mask == 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_dcc(struct radv_image *image)
|
|
|
|
{
|
|
|
|
return radv_image_can_enable_dcc_or_cmask(image) &&
|
2018-04-06 14:37:28 +01:00
|
|
|
radv_image_has_dcc(image);
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_cmask(struct radv_image *image)
|
|
|
|
{
|
2017-10-12 21:55:32 +01:00
|
|
|
if (image->surface.bpe > 8 && image->info.samples == 1) {
|
|
|
|
/* Do not enable CMASK for non-MSAA images (fast color clear)
|
|
|
|
* because 128 bit formats are not supported, but FMASK might
|
|
|
|
* still be used.
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-09-29 15:48:07 +01:00
|
|
|
return radv_image_can_enable_dcc_or_cmask(image) &&
|
|
|
|
image->info.levels == 1 &&
|
|
|
|
image->info.depth == 1 &&
|
|
|
|
!image->surface.is_linear;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_fmask(struct radv_image *image)
|
|
|
|
{
|
|
|
|
return image->info.samples > 1 && vk_format_is_color(image->vk_format);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_htile(struct radv_image *image)
|
|
|
|
{
|
|
|
|
return image->info.levels == 1 && vk_format_is_depth(image->vk_format);
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
VkResult
|
|
|
|
radv_image_create(VkDevice _device,
|
|
|
|
const struct radv_image_create_info *create_info,
|
|
|
|
const VkAllocationCallbacks* alloc,
|
|
|
|
VkImage *pImage)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
|
|
|
|
struct radv_image *image = NULL;
|
|
|
|
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
|
|
|
|
|
|
|
|
radv_assert(pCreateInfo->mipLevels > 0);
|
|
|
|
radv_assert(pCreateInfo->arrayLayers > 0);
|
|
|
|
radv_assert(pCreateInfo->samples > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.width > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.height > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.depth > 0);
|
|
|
|
|
2017-11-10 08:18:02 +00:00
|
|
|
image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
|
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
2016-10-07 00:16:09 +01:00
|
|
|
if (!image)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
image->type = pCreateInfo->imageType;
|
2017-05-02 00:49:14 +01:00
|
|
|
image->info.width = pCreateInfo->extent.width;
|
|
|
|
image->info.height = pCreateInfo->extent.height;
|
|
|
|
image->info.depth = pCreateInfo->extent.depth;
|
|
|
|
image->info.samples = pCreateInfo->samples;
|
2018-05-24 03:42:49 +01:00
|
|
|
image->info.storage_samples = pCreateInfo->samples;
|
2017-05-02 00:49:14 +01:00
|
|
|
image->info.array_size = pCreateInfo->arrayLayers;
|
|
|
|
image->info.levels = pCreateInfo->mipLevels;
|
2018-04-25 10:22:17 +01:00
|
|
|
image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
|
2017-05-02 00:49:14 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
image->vk_format = pCreateInfo->format;
|
|
|
|
image->tiling = pCreateInfo->tiling;
|
|
|
|
image->usage = pCreateInfo->usage;
|
2017-02-04 14:56:20 +00:00
|
|
|
image->flags = pCreateInfo->flags;
|
2016-12-17 20:25:32 +00:00
|
|
|
|
|
|
|
image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
|
2016-12-21 23:28:40 +00:00
|
|
|
if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
|
|
|
|
for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
|
2017-07-15 01:08:01 +01:00
|
|
|
if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHR)
|
|
|
|
image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
|
|
|
|
else
|
|
|
|
image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
|
2016-12-21 23:28:40 +00:00
|
|
|
}
|
2016-12-17 20:25:32 +00:00
|
|
|
|
2017-07-15 01:08:01 +01:00
|
|
|
image->shareable = vk_find_struct_const(pCreateInfo->pNext,
|
|
|
|
EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
|
2017-07-07 06:56:57 +01:00
|
|
|
if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
|
2017-07-28 22:08:10 +01:00
|
|
|
image->info.surf_index = &device->image_mrt_offset_counter;
|
2017-07-07 06:56:57 +01:00
|
|
|
}
|
2017-07-15 01:08:01 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_init_surface(device, &image->surface, create_info);
|
|
|
|
|
2017-05-02 00:58:33 +01:00
|
|
|
device->ws->surface_init(device->ws, &image->info, &image->surface);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-05-10 21:41:36 +01:00
|
|
|
image->size = image->surface.surf_size;
|
|
|
|
image->alignment = image->surface.surf_alignment;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-01-04 17:38:31 +00:00
|
|
|
if (!create_info->no_metadata_planes) {
|
|
|
|
/* Try to enable DCC first. */
|
|
|
|
if (radv_image_can_enable_dcc(image)) {
|
|
|
|
radv_image_alloc_dcc(image);
|
2018-04-17 15:05:15 +01:00
|
|
|
if (image->info.samples > 1) {
|
|
|
|
/* CMASK should be enabled because DCC fast
|
|
|
|
* clear with MSAA needs it.
|
|
|
|
*/
|
|
|
|
assert(radv_image_can_enable_cmask(image));
|
|
|
|
radv_image_alloc_cmask(device, image);
|
|
|
|
}
|
2018-01-04 17:38:31 +00:00
|
|
|
} else {
|
|
|
|
/* When DCC cannot be enabled, try CMASK. */
|
|
|
|
image->surface.dcc_size = 0;
|
|
|
|
if (radv_image_can_enable_cmask(image)) {
|
|
|
|
radv_image_alloc_cmask(device, image);
|
|
|
|
}
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-01-04 17:38:31 +00:00
|
|
|
/* Try to enable FMASK for multisampled images. */
|
|
|
|
if (radv_image_can_enable_fmask(image)) {
|
|
|
|
radv_image_alloc_fmask(device, image);
|
2017-09-29 15:48:07 +01:00
|
|
|
} else {
|
2018-01-04 17:38:31 +00:00
|
|
|
/* Otherwise, try to enable HTILE for depth surfaces. */
|
|
|
|
if (radv_image_can_enable_htile(image) &&
|
|
|
|
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
|
|
|
|
radv_image_alloc_htile(image);
|
|
|
|
image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
|
|
|
|
} else {
|
|
|
|
image->surface.htile_size = 0;
|
|
|
|
}
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
2018-01-04 17:38:31 +00:00
|
|
|
} else {
|
|
|
|
image->surface.dcc_size = 0;
|
|
|
|
image->surface.htile_size = 0;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
|
|
|
|
image->alignment = MAX2(image->alignment, 4096);
|
|
|
|
image->size = align64(image->size, image->alignment);
|
|
|
|
image->offset = 0;
|
|
|
|
|
|
|
|
image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
|
|
|
|
0, RADEON_FLAG_VIRTUAL);
|
|
|
|
if (!image->bo) {
|
|
|
|
vk_free2(&device->alloc, alloc, image);
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
|
2017-02-04 14:56:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
*pImage = radv_image_to_handle(image);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2017-07-12 10:29:52 +01:00
|
|
|
static void
|
|
|
|
radv_image_view_make_descriptor(struct radv_image_view *iview,
|
|
|
|
struct radv_device *device,
|
2017-08-21 04:56:33 +01:00
|
|
|
const VkComponentMapping *components,
|
2017-07-12 10:29:52 +01:00
|
|
|
bool is_storage_image)
|
|
|
|
{
|
2017-08-21 04:56:33 +01:00
|
|
|
struct radv_image *image = iview->image;
|
2017-07-12 10:29:52 +01:00
|
|
|
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
|
|
|
|
uint32_t blk_w;
|
|
|
|
uint32_t *descriptor;
|
2017-08-21 21:08:10 +01:00
|
|
|
uint32_t hw_level = 0;
|
2017-07-12 10:29:52 +01:00
|
|
|
|
|
|
|
if (is_storage_image) {
|
|
|
|
descriptor = iview->storage_descriptor;
|
|
|
|
} else {
|
|
|
|
descriptor = iview->descriptor;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
|
|
|
|
blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
|
|
|
|
|
2017-08-21 21:08:10 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
hw_level = iview->base_mip;
|
2017-07-12 10:29:52 +01:00
|
|
|
si_make_texture_descriptor(device, image, is_storage_image,
|
|
|
|
iview->type,
|
|
|
|
iview->vk_format,
|
2017-08-21 04:56:33 +01:00
|
|
|
components,
|
2017-08-21 21:08:10 +01:00
|
|
|
hw_level, hw_level + iview->level_count - 1,
|
2017-08-21 04:56:33 +01:00
|
|
|
iview->base_layer,
|
|
|
|
iview->base_layer + iview->layer_count - 1,
|
2017-07-12 10:29:52 +01:00
|
|
|
iview->extent.width,
|
|
|
|
iview->extent.height,
|
|
|
|
iview->extent.depth,
|
|
|
|
descriptor,
|
2017-11-15 11:08:29 +00:00
|
|
|
descriptor + 8);
|
2017-08-21 04:56:33 +01:00
|
|
|
|
|
|
|
const struct legacy_surf_level *base_level_info = NULL;
|
|
|
|
if (device->physical_device->rad_info.chip_class <= GFX9) {
|
|
|
|
if (is_stencil)
|
|
|
|
base_level_info = &image->surface.u.legacy.stencil_level[iview->base_mip];
|
|
|
|
else
|
|
|
|
base_level_info = &image->surface.u.legacy.level[iview->base_mip];
|
|
|
|
}
|
2017-07-12 10:29:52 +01:00
|
|
|
si_set_mutable_tex_desc_fields(device, image,
|
2017-08-21 04:56:33 +01:00
|
|
|
base_level_info,
|
|
|
|
iview->base_mip,
|
|
|
|
iview->base_mip,
|
2017-12-23 10:42:18 +00:00
|
|
|
blk_w, is_stencil, is_storage_image, descriptor);
|
2017-07-12 10:29:52 +01:00
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void
|
|
|
|
radv_image_view_init(struct radv_image_view *iview,
|
|
|
|
struct radv_device *device,
|
2017-06-25 21:25:47 +01:00
|
|
|
const VkImageViewCreateInfo* pCreateInfo)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
|
|
|
|
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
|
2017-07-12 10:29:52 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
switch (image->type) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
2017-05-02 00:49:14 +01:00
|
|
|
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
|
2016-10-07 00:16:09 +01:00
|
|
|
break;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
|
2017-05-02 00:49:14 +01:00
|
|
|
<= radv_minify(image->info.depth, range->baseMipLevel));
|
2016-10-07 00:16:09 +01:00
|
|
|
break;
|
2016-10-11 01:43:09 +01:00
|
|
|
default:
|
|
|
|
unreachable("bad VkImageType");
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
iview->image = image;
|
|
|
|
iview->bo = image->bo;
|
|
|
|
iview->type = pCreateInfo->viewType;
|
|
|
|
iview->vk_format = pCreateInfo->format;
|
|
|
|
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
|
|
|
|
|
2016-11-15 06:46:50 +00:00
|
|
|
if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
|
|
|
|
iview->vk_format = vk_format_stencil_only(iview->vk_format);
|
|
|
|
} else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
|
|
|
|
iview->vk_format = vk_format_depth_only(iview->vk_format);
|
|
|
|
}
|
|
|
|
|
2017-08-21 05:04:02 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
iview->extent = (VkExtent3D) {
|
|
|
|
.width = image->info.width,
|
|
|
|
.height = image->info.height,
|
|
|
|
.depth = image->info.depth,
|
|
|
|
};
|
|
|
|
} else {
|
|
|
|
iview->extent = (VkExtent3D) {
|
|
|
|
.width = radv_minify(image->info.width , range->baseMipLevel),
|
|
|
|
.height = radv_minify(image->info.height, range->baseMipLevel),
|
|
|
|
.depth = radv_minify(image->info.depth , range->baseMipLevel),
|
|
|
|
};
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-08-21 04:58:27 +01:00
|
|
|
if (iview->vk_format != image->vk_format) {
|
2018-01-29 04:15:09 +00:00
|
|
|
unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
|
|
|
|
unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
|
|
|
|
unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
|
|
|
|
unsigned img_bh = vk_format_get_blockheight(image->vk_format);
|
|
|
|
|
|
|
|
iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
|
|
|
|
iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
|
|
|
|
|
|
|
|
/* Comment ported from amdvlk -
|
|
|
|
* If we have the following image:
|
|
|
|
* Uncompressed pixels Compressed block sizes (4x4)
|
|
|
|
* mip0: 22 x 22 6 x 6
|
|
|
|
* mip1: 11 x 11 3 x 3
|
|
|
|
* mip2: 5 x 5 2 x 2
|
|
|
|
* mip3: 2 x 2 1 x 1
|
|
|
|
* mip4: 1 x 1 1 x 1
|
|
|
|
*
|
|
|
|
* On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
|
|
|
|
* calculating the degradation of the block sizes down the mip-chain as follows (straight-up
|
|
|
|
* divide-by-two integer math):
|
|
|
|
* mip0: 6x6
|
|
|
|
* mip1: 3x3
|
|
|
|
* mip2: 1x1
|
|
|
|
* mip3: 1x1
|
|
|
|
*
|
|
|
|
* This means that mip2 will be missing texels.
|
|
|
|
*
|
|
|
|
* Fix this by calculating the base mip's width and height, then convert that, and round it
|
|
|
|
* back up to get the level 0 size.
|
|
|
|
* Clamp the converted size between the original values, and next power of two, which
|
|
|
|
* means we don't oversize the image.
|
|
|
|
*/
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
vk_format_is_compressed(image->vk_format) &&
|
|
|
|
!vk_format_is_compressed(iview->vk_format)) {
|
|
|
|
unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
|
|
|
|
unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
|
|
|
|
unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
|
|
|
|
unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
|
|
|
|
|
|
|
|
lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
|
|
|
|
lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
|
|
|
|
|
|
|
|
lvl_width <<= range->baseMipLevel;
|
|
|
|
lvl_height <<= range->baseMipLevel;
|
|
|
|
|
|
|
|
iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
|
|
|
|
iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
|
|
|
|
}
|
2017-08-21 04:58:27 +01:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
iview->base_layer = range->baseArrayLayer;
|
|
|
|
iview->layer_count = radv_get_layerCount(image, range);
|
|
|
|
iview->base_mip = range->baseMipLevel;
|
2017-08-21 04:56:33 +01:00
|
|
|
iview->level_count = radv_get_levelCount(image, range);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-08-21 04:56:33 +01:00
|
|
|
radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, false);
|
|
|
|
radv_image_view_make_descriptor(iview, device, &pCreateInfo->components, true);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool radv_layout_has_htile(const struct radv_image *image,
|
2017-05-15 22:00:17 +01:00
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2018-04-06 15:17:26 +01:00
|
|
|
if (radv_image_is_tc_compat_htile(image))
|
2017-05-09 07:26:07 +01:00
|
|
|
return layout != VK_IMAGE_LAYOUT_GENERAL;
|
|
|
|
|
2018-04-06 14:37:28 +01:00
|
|
|
return radv_image_has_htile(image) &&
|
2017-05-15 00:23:24 +01:00
|
|
|
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
|
2017-05-15 22:00:17 +01:00
|
|
|
layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
|
|
|
|
queue_mask == (1u << RADV_QUEUE_GENERAL);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool radv_layout_is_htile_compressed(const struct radv_image *image,
|
2017-05-15 22:00:17 +01:00
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2018-04-06 15:17:26 +01:00
|
|
|
if (radv_image_is_tc_compat_htile(image))
|
2017-05-09 07:26:07 +01:00
|
|
|
return layout != VK_IMAGE_LAYOUT_GENERAL;
|
|
|
|
|
2018-04-06 14:37:28 +01:00
|
|
|
return radv_image_has_htile(image) &&
|
2017-05-15 00:23:24 +01:00
|
|
|
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
|
2017-05-15 22:00:17 +01:00
|
|
|
layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
|
|
|
|
queue_mask == (1u << RADV_QUEUE_GENERAL);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2016-12-26 23:57:36 +00:00
|
|
|
bool radv_layout_can_fast_clear(const struct radv_image *image,
|
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2016-12-29 23:11:19 +00:00
|
|
|
return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
|
2016-12-17 20:25:32 +00:00
|
|
|
queue_mask == (1u << RADV_QUEUE_GENERAL);
|
|
|
|
}
|
|
|
|
|
2017-12-28 01:54:10 +00:00
|
|
|
bool radv_layout_dcc_compressed(const struct radv_image *image,
|
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask)
|
|
|
|
{
|
|
|
|
/* Don't compress compute transfer dst, as image stores are not supported. */
|
|
|
|
if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
|
|
|
|
(queue_mask & (1u << RADV_QUEUE_COMPUTE)))
|
|
|
|
return false;
|
|
|
|
|
2018-04-11 20:34:43 +01:00
|
|
|
return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
|
2017-12-28 01:54:10 +00:00
|
|
|
}
|
|
|
|
|
2016-12-17 20:25:32 +00:00
|
|
|
|
2017-01-31 05:18:33 +00:00
|
|
|
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
|
|
|
|
{
|
|
|
|
if (!image->exclusive)
|
|
|
|
return image->queue_family_mask;
|
2017-07-15 01:08:01 +01:00
|
|
|
if (family == VK_QUEUE_FAMILY_EXTERNAL_KHR)
|
|
|
|
return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
|
2017-01-31 05:18:33 +00:00
|
|
|
if (family == VK_QUEUE_FAMILY_IGNORED)
|
|
|
|
return 1u << queue_family;
|
|
|
|
return 1u << family;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateImage(VkDevice device,
|
|
|
|
const VkImageCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkImage *pImage)
|
|
|
|
{
|
2018-01-04 17:38:32 +00:00
|
|
|
#ifdef ANDROID
|
|
|
|
const VkNativeBufferANDROID *gralloc_info =
|
|
|
|
vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
|
|
|
|
|
|
|
|
if (gralloc_info)
|
|
|
|
return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
|
|
|
|
pAllocator, pImage);
|
|
|
|
#endif
|
|
|
|
|
2017-11-16 16:27:01 +00:00
|
|
|
const struct wsi_image_create_info *wsi_info =
|
|
|
|
vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
|
|
|
|
bool scanout = wsi_info && wsi_info->scanout;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
return radv_image_create(device,
|
|
|
|
&(struct radv_image_create_info) {
|
|
|
|
.vk_info = pCreateInfo,
|
2017-11-16 16:27:01 +00:00
|
|
|
.scanout = scanout,
|
|
|
|
},
|
2016-10-07 00:16:09 +01:00
|
|
|
pAllocator,
|
|
|
|
pImage);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyImage(VkDevice _device, VkImage _image,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
2017-02-04 14:56:20 +00:00
|
|
|
RADV_FROM_HANDLE(radv_image, image, _image);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
if (!image)
|
2016-10-07 00:16:09 +01:00
|
|
|
return;
|
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
|
|
|
|
device->ws->buffer_destroy(image->bo);
|
|
|
|
|
2018-01-04 17:38:32 +00:00
|
|
|
if (image->owned_memory != VK_NULL_HANDLE)
|
|
|
|
radv_FreeMemory(_device, image->owned_memory, pAllocator);
|
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
vk_free2(&device->alloc, pAllocator, image);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void radv_GetImageSubresourceLayout(
|
2017-08-15 06:35:52 +01:00
|
|
|
VkDevice _device,
|
2016-10-07 00:16:09 +01:00
|
|
|
VkImage _image,
|
|
|
|
const VkImageSubresource* pSubresource,
|
|
|
|
VkSubresourceLayout* pLayout)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_image, image, _image);
|
2017-08-15 06:35:52 +01:00
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
2016-10-07 00:16:09 +01:00
|
|
|
int level = pSubresource->mipLevel;
|
|
|
|
int layer = pSubresource->arrayLayer;
|
2017-05-10 21:05:52 +01:00
|
|
|
struct radeon_surf *surface = &image->surface;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-08-15 06:35:52 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
|
|
|
|
pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
|
|
|
|
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
|
|
|
|
pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
|
|
|
|
pLayout->size = surface->u.gfx9.surf_slice_size;
|
|
|
|
if (image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pLayout->size *= u_minify(image->info.depth, level);
|
|
|
|
} else {
|
2017-11-14 18:31:39 +00:00
|
|
|
pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
|
2017-08-15 06:35:52 +01:00
|
|
|
pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
|
2017-11-14 18:31:39 +00:00
|
|
|
pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
|
|
|
pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
|
|
|
pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
2017-08-15 06:35:52 +01:00
|
|
|
if (image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pLayout->size *= u_minify(image->info.depth, level);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateImageView(VkDevice _device,
|
|
|
|
const VkImageViewCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkImageView *pView)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
struct radv_image_view *view;
|
|
|
|
|
2016-10-14 04:36:45 +01:00
|
|
|
view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
|
2016-10-07 00:16:09 +01:00
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (view == NULL)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-06-25 21:25:47 +01:00
|
|
|
radv_image_view_init(view, device, pCreateInfo);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
*pView = radv_image_view_to_handle(view);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyImageView(VkDevice _device, VkImageView _iview,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_image_view, iview, _iview);
|
|
|
|
|
|
|
|
if (!iview)
|
|
|
|
return;
|
2016-10-14 04:36:45 +01:00
|
|
|
vk_free2(&device->alloc, pAllocator, iview);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void radv_buffer_view_init(struct radv_buffer_view *view,
|
|
|
|
struct radv_device *device,
|
2017-09-12 18:08:45 +01:00
|
|
|
const VkBufferViewCreateInfo* pCreateInfo)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
|
|
|
|
|
|
|
|
view->bo = buffer->bo;
|
|
|
|
view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
|
|
|
|
buffer->size - pCreateInfo->offset : pCreateInfo->range;
|
|
|
|
view->vk_format = pCreateInfo->format;
|
|
|
|
|
|
|
|
radv_make_buffer_descriptor(device, buffer, view->vk_format,
|
|
|
|
pCreateInfo->offset, view->range, view->state);
|
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateBufferView(VkDevice _device,
|
|
|
|
const VkBufferViewCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkBufferView *pView)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
struct radv_buffer_view *view;
|
|
|
|
|
2016-10-14 04:36:45 +01:00
|
|
|
view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
|
2016-10-07 00:16:09 +01:00
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (!view)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-09-12 18:08:45 +01:00
|
|
|
radv_buffer_view_init(view, device, pCreateInfo);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
*pView = radv_buffer_view_to_handle(view);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
|
|
|
|
|
|
|
|
if (!view)
|
|
|
|
return;
|
|
|
|
|
2016-10-14 04:36:45 +01:00
|
|
|
vk_free2(&device->alloc, pAllocator, view);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|