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ac/surface: move cmask_size/alignment into radeon_surf 

cmask_size is changed to uint32_t because it can't be greater than 4GB.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
Marek Olšák 2018-06-21 22:50:51 -04:00
parent 2d64a68c6f
commit 3da693b7d9
4 changed files with 17 additions and 17 deletions
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6
src/amd/common/ac_surface.c
View File

@ -1286,8 +1286,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned;
surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned;
surf->u.gfx9.cmask_size = cout.cmaskBytes;
surf->u.gfx9.cmask_alignment = cout.baseAlign;
surf->cmask_size = cout.cmaskBytes;
surf->cmask_alignment = cout.baseAlign;
}
}
@ -1428,7 +1428,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
surf->htile_slice_size = 0;
surf->u.gfx9.surf_offset = 0;
surf->u.gfx9.stencil_offset = 0;
surf->u.gfx9.cmask_size = 0;
surf->cmask_size = 0;
/* Calculate texture layout information. */
r = gfx9_compute_miptree(addrlib, config, surf, compressed,

18
src/amd/common/ac_surface.h
View File

@ -150,9 +150,6 @@ struct gfx9_surf_layout {
uint16_t dcc_pitch_max; /* (mip chain pitch - 1) */
uint64_t stencil_offset; /* separate stencil */
uint64_t cmask_size;
uint32_t cmask_alignment;
};
struct radeon_surf {
@ -196,17 +193,20 @@ struct radeon_surf {
uint64_t surf_size;
uint64_t fmask_size;
/* DCC and HTILE are very small. */
uint32_t dcc_size;
uint32_t htile_size;
uint32_t htile_slice_size;
uint32_t surf_alignment;
uint32_t fmask_alignment;
/* DCC and HTILE are very small. */
uint32_t dcc_size;
uint32_t dcc_alignment;
uint32_t htile_size;
uint32_t htile_slice_size;
uint32_t htile_alignment;
uint32_t cmask_size;
uint32_t cmask_alignment;
union {
/* R600-VI return values.
*

4
src/amd/vulkan/radv_image.c
View File

@ -772,8 +772,8 @@ radv_image_get_cmask_info(struct radv_device *device,
unsigned cl_width, cl_height;
if (device->physical_device->rad_info.chip_class >= GFX9) {
out->alignment = image->surface.u.gfx9.cmask_alignment;
out->size = image->surface.u.gfx9.cmask_size;
out->alignment = image->surface.cmask_alignment;
out->size = image->surface.cmask_size;
return;
}

6
src/gallium/drivers/radeonsi/si_texture.c
View File

@ -1050,11 +1050,11 @@ void si_print_texture_info(struct si_screen *sscreen,
}
if (tex->cmask.size) {
u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
tex->cmask.offset,
tex->surface.u.gfx9.cmask_size,
tex->surface.u.gfx9.cmask_alignment,
tex->surface.cmask_size,
tex->surface.cmask_alignment,
tex->surface.u.gfx9.cmask.rb_aligned,
tex->surface.u.gfx9.cmask.pipe_aligned);
}