radv: remove some members of radeon surface.
We would be storing this info twice per image, no need to, remove it from the surface struct. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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7e8d0a402b
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052487be4c
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@ -966,7 +966,7 @@ static void radv_set_optimal_micro_tile_mode(struct radv_device *device,
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{
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struct radv_image *image = att->attachment->image;
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uint32_t tile_mode_index;
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if (image->surface.nsamples <= 1)
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if (image->info.samples <= 1)
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return;
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if (image->surface.micro_tile_mode != micro_tile_mode) {
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@ -67,22 +67,16 @@ radv_init_surface(struct radv_device *device,
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is_depth = vk_format_has_depth(desc);
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is_stencil = vk_format_has_stencil(desc);
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surface->npix_x = pCreateInfo->extent.width;
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surface->npix_y = pCreateInfo->extent.height;
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surface->npix_z = pCreateInfo->extent.depth;
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surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
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surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
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surface->blk_d = 1;
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surface->array_size = pCreateInfo->arrayLayers;
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surface->last_level = pCreateInfo->mipLevels - 1;
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surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
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/* align byte per element on dword */
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if (surface->bpe == 3) {
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surface->bpe = 4;
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}
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surface->nsamples = pCreateInfo->samples ? pCreateInfo->samples : 1;
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surface->flags = RADEON_SURF_SET(array_mode, MODE);
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switch (pCreateInfo->imageType){
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@ -467,14 +461,13 @@ radv_image_get_fmask_info(struct radv_device *device,
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{
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/* FMASK is allocated like an ordinary texture. */
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struct radeon_surf fmask = image->surface;
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struct radeon_surf_info info = image->info;
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memset(out, 0, sizeof(*out));
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fmask.bo_alignment = 0;
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fmask.bo_size = 0;
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fmask.nsamples = 1;
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fmask.flags |= RADEON_SURF_FMASK;
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info.samples = 1;
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/* Force 2D tiling if it wasn't set. This may occur when creating
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* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
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* destination buffer must have an FMASK too. */
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@ -495,7 +488,7 @@ radv_image_get_fmask_info(struct radv_device *device,
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return;
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}
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device->ws->surface_init(device->ws, &fmask);
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device->ws->surface_init(device->ws, &info, &fmask);
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assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
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out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
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@ -553,8 +546,8 @@ radv_image_get_cmask_info(struct radv_device *device,
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unsigned base_align = num_pipes * pipe_interleave_bytes;
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unsigned width = align(image->surface.npix_x, cl_width*8);
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unsigned height = align(image->surface.npix_y, cl_height*8);
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unsigned width = align(image->info.width, cl_width*8);
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unsigned height = align(image->info.height, cl_height*8);
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unsigned slice_elements = (width * height) / (8*8);
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/* Each element of CMASK is a nibble. */
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@ -656,7 +649,7 @@ radv_image_create(VkDevice _device,
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radv_init_surface(device, &image->surface, create_info);
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device->ws->surface_init(device->ws, &image->surface);
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device->ws->surface_init(device->ws, &image->info, &image->surface);
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image->size = image->surface.bo_size;
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image->alignment = image->surface.bo_alignment;
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@ -184,16 +184,10 @@ struct radeon_surf_level {
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/* surface defintions from the winsys */
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struct radeon_surf {
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/* These are inputs to the calculator. */
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uint32_t npix_x;
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uint32_t npix_y;
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uint32_t npix_z;
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uint32_t blk_w;
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uint32_t blk_h;
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uint32_t blk_d;
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uint32_t array_size;
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uint32_t last_level;
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uint32_t bpe;
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uint32_t nsamples;
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uint32_t flags;
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/* These are return values. Some of them can be set by the caller, but
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@ -343,6 +337,7 @@ struct radeon_winsys {
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void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
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int (*surface_init)(struct radeon_winsys *ws,
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const struct radeon_surf_info *surf_info,
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struct radeon_surf *surf);
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int (*surface_best)(struct radeon_winsys *ws,
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@ -47,7 +47,8 @@
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#endif
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static int radv_amdgpu_surface_sanity(const struct radeon_surf *surf)
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static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
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const struct radeon_surf *surf)
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{
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unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
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@ -55,14 +56,14 @@ static int radv_amdgpu_surface_sanity(const struct radeon_surf *surf)
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return -EINVAL;
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/* all dimension must be at least 1 ! */
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if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
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!surf->array_size)
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if (!surf_info->width || !surf_info->height || !surf_info->depth ||
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!surf_info->array_size)
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return -EINVAL;
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if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
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return -EINVAL;
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switch (surf->nsamples) {
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switch (surf_info->samples) {
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case 1:
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case 2:
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case 4:
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@ -74,24 +75,24 @@ static int radv_amdgpu_surface_sanity(const struct radeon_surf *surf)
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switch (type) {
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case RADEON_SURF_TYPE_1D:
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if (surf->npix_y > 1)
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if (surf_info->height > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D:
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case RADEON_SURF_TYPE_CUBEMAP:
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if (surf->npix_z > 1 || surf->array_size > 1)
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if (surf_info->depth > 1 || surf_info->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_3D:
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if (surf->array_size > 1)
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if (surf_info->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_1D_ARRAY:
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if (surf->npix_y > 1)
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if (surf_info->height > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D_ARRAY:
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if (surf->npix_z > 1)
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if (surf_info->depth > 1)
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return -EINVAL;
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break;
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default:
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@ -158,6 +159,7 @@ ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family,
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}
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static int radv_compute_level(ADDR_HANDLE addrlib,
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const struct radeon_surf_info *surf_info,
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struct radeon_surf *surf, bool is_stencil,
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unsigned level, unsigned type, bool compressed,
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ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
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@ -169,15 +171,15 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
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ADDR_E_RETURNCODE ret;
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AddrSurfInfoIn->mipLevel = level;
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AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
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AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
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AddrSurfInfoIn->width = u_minify(surf_info->width, level);
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AddrSurfInfoIn->height = u_minify(surf_info->height, level);
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if (type == RADEON_SURF_TYPE_3D)
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AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
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AddrSurfInfoIn->numSlices = u_minify(surf_info->depth, level);
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else if (type == RADEON_SURF_TYPE_CUBEMAP)
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AddrSurfInfoIn->numSlices = 6;
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else
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AddrSurfInfoIn->numSlices = surf->array_size;
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AddrSurfInfoIn->numSlices = surf_info->array_size;
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if (level > 0) {
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/* Set the base level pitch. This is needed for calculation
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@ -202,9 +204,9 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
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surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
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surf_level->slice_size = AddrSurfInfoOut->sliceSize;
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surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
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surf_level->npix_x = u_minify(surf->npix_x, level);
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surf_level->npix_y = u_minify(surf->npix_y, level);
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surf_level->npix_z = u_minify(surf->npix_z, level);
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surf_level->npix_x = u_minify(surf_info->width, level);
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surf_level->npix_y = u_minify(surf_info->height, level);
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surf_level->npix_z = u_minify(surf_info->depth, level);
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surf_level->nblk_x = AddrSurfInfoOut->pitch;
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surf_level->nblk_y = AddrSurfInfoOut->height;
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if (type == RADEON_SURF_TYPE_3D)
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@ -312,6 +314,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
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}
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static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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const struct radeon_surf_info *surf_info,
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struct radeon_surf *surf)
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{
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struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
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@ -324,8 +327,9 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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ADDR_TILEINFO AddrTileInfoIn = {0};
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ADDR_TILEINFO AddrTileInfoOut = {0};
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int r;
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uint32_t last_level = surf_info->levels - 1;
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r = radv_amdgpu_surface_sanity(surf);
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r = radv_amdgpu_surface_sanity(surf_info, surf);
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if (r)
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return r;
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@ -340,7 +344,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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/* MSAA and FMASK require 2D tiling. */
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if (surf->nsamples > 1 ||
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if (surf_info->samples > 1 ||
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(surf->flags & RADEON_SURF_FMASK))
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mode = RADEON_SURF_MODE_2D;
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@ -381,7 +385,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
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}
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf_info->samples;
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AddrSurfInfoIn.tileIndex = -1;
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/* Set the micro tile type. */
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@ -396,7 +400,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
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AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
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AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
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AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
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AddrSurfInfoIn.flags.pow2Pad = last_level > 0;
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AddrSurfInfoIn.flags.opt4Space = 1;
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/* DCC notes:
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@ -408,8 +412,8 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
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!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!compressed && AddrDccIn.numSamples <= 1 &&
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((surf->array_size == 1 && surf->npix_z == 1) ||
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surf->last_level == 0);
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((surf_info->array_size == 1 && surf_info->depth == 1) ||
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last_level == 0);
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AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
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AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
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@ -421,7 +425,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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* TODO: update addrlib to a newer version, remove this, and
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* use flags.matchStencilTileCfg = 1 as an alternative fix.
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*/
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if (surf->last_level > 0)
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if (last_level > 0)
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AddrSurfInfoIn.flags.noStencil = 1;
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/* Set preferred macrotile parameters. This is usually required
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@ -482,8 +486,8 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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surf->htile_alignment = 1;
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/* Calculate texture layout information. */
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for (level = 0; level <= surf->last_level; level++) {
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r = radv_compute_level(ws->addrlib, surf, false, level, type, compressed,
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for (level = 0; level <= last_level; level++) {
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r = radv_compute_level(ws->addrlib, surf_info, surf, false, level, type, compressed,
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&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
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if (r)
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break;
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@ -515,8 +519,8 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
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AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
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for (level = 0; level <= surf->last_level; level++) {
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r = radv_compute_level(ws->addrlib, surf, true, level, type, compressed,
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for (level = 0; level <= last_level; level++) {
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r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
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&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
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if (r)
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return r;
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@ -540,7 +544,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
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* complicated.
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*/
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#if 0
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if (surf->dcc_size && surf->last_level > 0) {
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if (surf->dcc_size && last_level > 0) {
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surf->dcc_size = align64(surf->bo_size >> 8,
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ws->info.pipe_interleave_bytes *
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ws->info.num_tile_pipes);
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