2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2017-08-30 14:12:20 +01:00
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#include "radv_debug.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_private.h"
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#include "vk_format.h"
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2017-07-15 01:08:01 +01:00
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#include "vk_util.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_radeon_winsys.h"
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#include "sid.h"
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#include "util/debug.h"
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2017-07-07 06:56:57 +01:00
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#include "util/u_atomic.h"
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2020-06-02 00:44:52 +01:00
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#include "vulkan/util/vk_format.h"
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2020-06-01 23:45:14 +01:00
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#include "gfx10_format_table.h"
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2016-10-07 00:16:09 +01:00
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static unsigned
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2017-08-22 03:47:09 +01:00
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radv_choose_tiling(struct radv_device *device,
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2019-09-24 15:33:39 +01:00
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const VkImageCreateInfo *pCreateInfo,
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VkFormat format)
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2016-10-07 00:16:09 +01:00
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{
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
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assert(pCreateInfo->samples <= 1);
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return RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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2019-09-24 15:33:39 +01:00
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if (!vk_format_is_compressed(format) &&
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!vk_format_is_depth_or_stencil(format)
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2019-05-15 03:16:20 +01:00
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&& device->physical_device->rad_info.chip_class <= GFX8) {
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2017-08-22 03:47:09 +01:00
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/* this causes hangs in some VK CTS tests on GFX9. */
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2017-08-21 05:10:21 +01:00
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/* Textures with a very small height are recommended to be linear. */
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if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
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/* Only very thin and long 2D textures should benefit from
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* linear_aligned. */
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(pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
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return RADEON_SURF_MODE_LINEAR_ALIGNED;
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}
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2017-04-13 05:12:28 +01:00
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2016-10-07 00:16:09 +01:00
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/* MSAA resources must be 2D tiled. */
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if (pCreateInfo->samples > 1)
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return RADEON_SURF_MODE_2D;
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return RADEON_SURF_MODE_2D;
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}
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2018-03-21 20:30:40 +00:00
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static bool
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2018-04-06 15:07:22 +01:00
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radv_use_tc_compat_htile_for_image(struct radv_device *device,
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2019-09-24 15:33:39 +01:00
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const VkImageCreateInfo *pCreateInfo,
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VkFormat format)
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2018-03-21 20:30:40 +00:00
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{
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/* TC-compat HTILE is only available for GFX8+. */
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2019-05-15 03:16:20 +01:00
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if (device->physical_device->rad_info.chip_class < GFX8)
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2018-03-21 20:30:40 +00:00
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return false;
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2020-01-16 01:33:35 +00:00
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if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
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2018-03-21 20:30:40 +00:00
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return false;
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
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return false;
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if (pCreateInfo->mipLevels > 1)
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return false;
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2020-03-31 09:35:00 +01:00
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/* Do not enable TC-compatible HTILE if the image isn't readable by a
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* shader because no texture fetches will happen.
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*/
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if (!(pCreateInfo->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
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VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
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VK_IMAGE_USAGE_TRANSFER_SRC_BIT)))
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return false;
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2018-03-21 20:30:40 +00:00
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/* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
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2019-07-11 10:54:24 +01:00
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* tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
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*/
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2018-03-21 20:30:40 +00:00
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if (pCreateInfo->samples >= 2 &&
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2019-09-24 15:33:39 +01:00
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(format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
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(format == VK_FORMAT_D32_SFLOAT &&
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2019-07-11 10:54:24 +01:00
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device->physical_device->rad_info.chip_class == GFX10)))
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2018-03-21 20:30:40 +00:00
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return false;
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2018-03-21 20:30:42 +00:00
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/* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
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* supports 32-bit. Though, it's possible to enable TC-compat for
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* 16-bit depth surfaces if no Z planes are compressed.
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*/
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2019-09-24 15:33:39 +01:00
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if (format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
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format != VK_FORMAT_D32_SFLOAT &&
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format != VK_FORMAT_D16_UNORM)
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2018-03-21 20:30:42 +00:00
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return false;
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2018-03-21 20:30:40 +00:00
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2018-09-28 14:05:24 +01:00
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if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
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2019-10-15 08:26:20 +01:00
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const struct VkImageFormatListCreateInfo *format_list =
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(const struct VkImageFormatListCreateInfo *)
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2018-09-28 14:05:24 +01:00
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vk_find_struct_const(pCreateInfo->pNext,
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2019-10-15 08:26:20 +01:00
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IMAGE_FORMAT_LIST_CREATE_INFO);
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2018-09-28 14:05:24 +01:00
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/* We have to ignore the existence of the list if viewFormatCount = 0 */
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if (format_list && format_list->viewFormatCount) {
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/* compatibility is transitive, so we only need to check
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* one format with everything else.
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*/
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for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
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2019-06-08 22:51:16 +01:00
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if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
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continue;
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2019-09-24 15:33:39 +01:00
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if (format != format_list->pViewFormats[i])
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2018-09-28 14:05:24 +01:00
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return false;
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}
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} else {
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return false;
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}
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}
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2018-03-21 20:30:40 +00:00
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return true;
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}
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2019-05-13 13:09:55 +01:00
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static bool
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radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
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{
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2019-12-31 20:19:20 +00:00
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if (info->bo_metadata) {
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if (device->physical_device->rad_info.chip_class >= GFX9)
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return info->bo_metadata->u.gfx9.scanout;
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else
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return info->bo_metadata->u.legacy.scanout;
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2019-05-13 13:09:55 +01:00
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}
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2019-12-31 20:19:20 +00:00
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return info->scanout;
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2019-05-13 13:09:55 +01:00
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}
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2020-05-24 12:57:02 +01:00
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static bool
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radv_image_use_fast_clear_for_image(const struct radv_image *image)
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{
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if (image->info.samples <= 1 &&
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image->info.width * image->info.height <= 512 * 512) {
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/* Do not enable CMASK or DCC for small surfaces where the cost
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* of the eliminate pass can be higher than the benefit of fast
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* clear. RadeonSI does this, but the image threshold is
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* different.
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*/
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return false;
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}
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return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
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(image->exclusive || image->queue_family_mask == 1);
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}
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2018-03-30 15:46:14 +01:00
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static bool
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radv_use_dcc_for_image(struct radv_device *device,
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2018-11-26 15:26:37 +00:00
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const struct radv_image *image,
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2019-09-24 15:33:39 +01:00
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const VkImageCreateInfo *pCreateInfo,
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VkFormat format)
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2018-03-30 15:46:14 +01:00
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{
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bool dcc_compatible_formats;
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bool blendable;
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/* DCC (Delta Color Compression) is only available for GFX8+. */
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2019-05-15 03:16:20 +01:00
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if (device->physical_device->rad_info.chip_class < GFX8)
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2018-03-30 15:46:14 +01:00
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return false;
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if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
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return false;
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2019-06-12 23:57:16 +01:00
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if (image->shareable)
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2018-05-10 04:40:21 +01:00
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return false;
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2019-08-16 00:13:00 +01:00
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/* TODO: Enable DCC for storage images. */
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2020-01-16 01:33:35 +00:00
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if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
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2018-03-30 15:46:14 +01:00
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return false;
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if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
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return false;
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2019-09-24 15:33:39 +01:00
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if (vk_format_is_subsampled(format) ||
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vk_format_get_plane_count(format) > 1)
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2018-07-15 19:09:28 +01:00
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return false;
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2020-05-24 12:57:02 +01:00
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if (!radv_image_use_fast_clear_for_image(image))
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return false;
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2019-06-20 08:17:37 +01:00
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/* TODO: Enable DCC for mipmaps on GFX9+. */
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2019-07-01 15:31:01 +01:00
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if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
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2019-06-20 08:17:37 +01:00
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device->physical_device->rad_info.chip_class >= GFX9)
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return false;
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2019-07-01 15:31:00 +01:00
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/* Do not enable DCC for mipmapped arrays because performance is worse. */
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if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
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return false;
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2018-04-25 09:56:15 +01:00
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/* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
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* 2x can be enabled with an option.
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*/
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if (pCreateInfo->samples > 2 ||
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(pCreateInfo->samples == 2 &&
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!device->physical_device->dcc_msaa_allowed))
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2018-03-30 15:46:14 +01:00
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return false;
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/* Determine if the formats are DCC compatible. */
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dcc_compatible_formats =
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2019-09-24 15:33:39 +01:00
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radv_is_colorbuffer_format_supported(format,
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2018-03-30 15:46:14 +01:00
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&blendable);
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if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
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2019-10-15 08:26:20 +01:00
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const struct VkImageFormatListCreateInfo *format_list =
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(const struct VkImageFormatListCreateInfo *)
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2018-03-30 15:46:14 +01:00
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vk_find_struct_const(pCreateInfo->pNext,
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2019-10-15 08:26:20 +01:00
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IMAGE_FORMAT_LIST_CREATE_INFO);
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2018-03-30 15:46:14 +01:00
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/* We have to ignore the existence of the list if viewFormatCount = 0 */
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if (format_list && format_list->viewFormatCount) {
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/* compatibility is transitive, so we only need to check
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* one format with everything else. */
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for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
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2019-06-08 22:51:16 +01:00
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if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
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continue;
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2019-09-24 15:33:39 +01:00
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if (!radv_dcc_formats_compatible(format,
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2018-03-30 15:46:14 +01:00
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format_list->pViewFormats[i]))
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dcc_compatible_formats = false;
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}
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} else {
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dcc_compatible_formats = false;
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}
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}
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if (!dcc_compatible_formats)
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return false;
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return true;
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}
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2020-05-24 10:57:09 +01:00
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static inline bool
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radv_use_fmask_for_image(const struct radv_image *image)
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{
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return image->info.samples > 1 &&
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image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
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}
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2020-05-24 13:00:05 +01:00
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static inline bool
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radv_use_htile_for_image(const struct radv_image *image)
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{
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return image->info.levels == 1 &&
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image->info.width * image->info.height >= 8 * 8;
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}
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2018-11-14 15:24:02 +00:00
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static bool
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radv_use_tc_compat_cmask_for_image(struct radv_device *device,
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struct radv_image *image)
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{
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if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
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return false;
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/* TC-compat CMASK is only available for GFX8+. */
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if (device->physical_device->rad_info.chip_class < GFX8)
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return false;
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if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
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return false;
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if (radv_image_has_dcc(image))
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return false;
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if (!radv_image_has_cmask(image))
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return false;
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return true;
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}
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|
2019-09-24 12:23:36 +01:00
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static uint32_t si_get_bo_metadata_word1(const struct radv_device *device)
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{
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return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
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}
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static bool
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radv_is_valid_opaque_metadata(const struct radv_device *device,
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const struct radeon_bo_metadata *md)
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{
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if (md->metadata[0] != 1 ||
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md->metadata[1] != si_get_bo_metadata_word1(device))
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return false;
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if (md->size_metadata < 40)
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return false;
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|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-05-13 13:09:55 +01:00
|
|
|
static void
|
2019-09-23 15:42:39 +01:00
|
|
|
radv_patch_surface_from_metadata(struct radv_device *device,
|
|
|
|
struct radeon_surf *surface,
|
|
|
|
const struct radeon_bo_metadata *md)
|
2019-05-13 13:09:55 +01:00
|
|
|
{
|
2019-09-23 15:42:39 +01:00
|
|
|
surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
|
|
|
|
|
2019-05-13 13:09:55 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
if (md->u.gfx9.swizzle_mode > 0)
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
|
|
|
|
else
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
|
|
|
|
|
|
|
|
surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
|
|
|
|
} else {
|
|
|
|
surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
|
|
|
|
surface->u.legacy.bankw = md->u.legacy.bankw;
|
|
|
|
surface->u.legacy.bankh = md->u.legacy.bankh;
|
|
|
|
surface->u.legacy.tile_split = md->u.legacy.tile_split;
|
|
|
|
surface->u.legacy.mtilea = md->u.legacy.mtilea;
|
|
|
|
surface->u.legacy.num_banks = md->u.legacy.num_banks;
|
|
|
|
|
|
|
|
if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
|
|
|
|
else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
|
|
|
|
else
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-24 12:23:36 +01:00
|
|
|
static VkResult
|
|
|
|
radv_patch_image_dimensions(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
const struct radv_image_create_info *create_info,
|
|
|
|
struct ac_surf_info *image_info)
|
|
|
|
{
|
|
|
|
unsigned width = image->info.width;
|
|
|
|
unsigned height = image->info.height;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* minigbm sometimes allocates bigger images which is going to result in
|
|
|
|
* weird strides and other properties. Lets be lenient where possible and
|
|
|
|
* fail it on GFX10 (as we cannot cope there).
|
|
|
|
*
|
|
|
|
* Example hack: https://chromium-review.googlesource.com/c/chromiumos/platform/minigbm/+/1457777/
|
|
|
|
*/
|
|
|
|
if (create_info->bo_metadata &&
|
|
|
|
radv_is_valid_opaque_metadata(device, create_info->bo_metadata)) {
|
|
|
|
const struct radeon_bo_metadata *md = create_info->bo_metadata;
|
|
|
|
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX10) {
|
|
|
|
width = G_00A004_WIDTH_LO(md->metadata[3]) +
|
|
|
|
(G_00A008_WIDTH_HI(md->metadata[4]) << 2) + 1;
|
|
|
|
height = S_00A008_HEIGHT(md->metadata[4]) + 1;
|
|
|
|
} else {
|
|
|
|
width = G_008F18_WIDTH(md->metadata[4]) + 1;
|
|
|
|
height = G_008F18_HEIGHT(md->metadata[4]) + 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (image->info.width == width && image->info.height == height)
|
|
|
|
return VK_SUCCESS;
|
|
|
|
|
|
|
|
if (width < image->info.width || height < image->info.height) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"The imported image has smaller dimensions than the internal\n"
|
|
|
|
"dimensions. Using it is going to fail badly, so we reject\n"
|
|
|
|
"this import.\n"
|
|
|
|
"(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
|
|
|
|
image->info.width, image->info.height, width, height);
|
|
|
|
return VK_ERROR_INVALID_EXTERNAL_HANDLE;
|
|
|
|
} else if (device->physical_device->rad_info.chip_class >= GFX10) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"Tried to import an image with inconsistent width on GFX10.\n"
|
|
|
|
"As GFX10 has no separate stride fields we cannot cope with\n"
|
|
|
|
"an inconsistency in width and will fail this import.\n"
|
|
|
|
"(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
|
|
|
|
image->info.width, image->info.height, width, height);
|
|
|
|
return VK_ERROR_INVALID_EXTERNAL_HANDLE;
|
|
|
|
} else {
|
|
|
|
fprintf(stderr,
|
|
|
|
"Tried to import an image with inconsistent width on pre-GFX10.\n"
|
|
|
|
"As GFX10 has no separate stride fields we cannot cope with\n"
|
|
|
|
"an inconsistency and would fail on GFX10.\n"
|
|
|
|
"(internal dimensions: %d x %d, external dimensions: %d x %d)\n",
|
|
|
|
image->info.width, image->info.height, width, height);
|
|
|
|
}
|
|
|
|
image_info->width = width;
|
|
|
|
image_info->height = height;
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static VkResult
|
2019-09-23 15:42:39 +01:00
|
|
|
radv_patch_image_from_extra_info(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
2019-09-24 12:23:36 +01:00
|
|
|
const struct radv_image_create_info *create_info,
|
|
|
|
struct ac_surf_info *image_info)
|
2019-09-23 15:42:39 +01:00
|
|
|
{
|
2019-09-24 12:23:36 +01:00
|
|
|
VkResult result = radv_patch_image_dimensions(device, image, create_info, image_info);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
|
|
|
|
2019-09-23 15:42:39 +01:00
|
|
|
for (unsigned plane = 0; plane < image->plane_count; ++plane) {
|
|
|
|
if (create_info->bo_metadata) {
|
|
|
|
radv_patch_surface_from_metadata(device, &image->planes[plane].surface,
|
|
|
|
create_info->bo_metadata);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (radv_surface_has_scanout(device, create_info)) {
|
|
|
|
image->planes[plane].surface.flags |= RADEON_SURF_SCANOUT;
|
|
|
|
image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC;
|
|
|
|
|
|
|
|
image->info.surf_index = NULL;
|
|
|
|
}
|
|
|
|
}
|
2019-09-24 12:23:36 +01:00
|
|
|
return VK_SUCCESS;
|
2019-09-23 15:42:39 +01:00
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
static int
|
|
|
|
radv_init_surface(struct radv_device *device,
|
2018-11-26 15:26:37 +00:00
|
|
|
const struct radv_image *image,
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radeon_surf *surface,
|
2018-07-16 19:51:26 +01:00
|
|
|
unsigned plane_id,
|
2019-09-24 15:33:39 +01:00
|
|
|
const VkImageCreateInfo *pCreateInfo,
|
|
|
|
VkFormat image_format)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2019-09-24 15:33:39 +01:00
|
|
|
unsigned array_mode = radv_choose_tiling(device, pCreateInfo, image_format);
|
|
|
|
VkFormat format = vk_format_get_plane_format(image_format, plane_id);
|
2018-07-16 19:51:26 +01:00
|
|
|
const struct vk_format_description *desc = vk_format_description(format);
|
2018-03-30 15:46:14 +01:00
|
|
|
bool is_depth, is_stencil;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
is_depth = vk_format_has_depth(desc);
|
|
|
|
is_stencil = vk_format_has_stencil(desc);
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
surface->blk_w = vk_format_get_blockwidth(format);
|
|
|
|
surface->blk_h = vk_format_get_blockheight(format);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
|
2016-10-07 00:16:09 +01:00
|
|
|
/* align byte per element on dword */
|
|
|
|
if (surface->bpe == 3) {
|
|
|
|
surface->bpe = 4;
|
|
|
|
}
|
2019-09-23 15:42:39 +01:00
|
|
|
|
|
|
|
surface->flags = RADEON_SURF_SET(array_mode, MODE);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
switch (pCreateInfo->imageType){
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
if (pCreateInfo->arrayLayers > 1)
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
|
|
|
|
else
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
|
|
|
|
break;
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
if (pCreateInfo->arrayLayers > 1)
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
|
|
|
|
else
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
|
|
|
|
break;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unhandled image type");
|
|
|
|
}
|
|
|
|
|
2020-05-24 11:50:55 +01:00
|
|
|
/* Required for clearing/initializing a specific layer on GFX8. */
|
|
|
|
surface->flags |= RADEON_SURF_CONTIGUOUS_DCC_LAYERS;
|
|
|
|
|
2020-05-02 21:01:44 +01:00
|
|
|
if (is_depth) {
|
2016-10-07 00:16:09 +01:00
|
|
|
surface->flags |= RADEON_SURF_ZBUFFER;
|
2020-05-24 13:00:05 +01:00
|
|
|
if (!radv_use_htile_for_image(image) ||
|
|
|
|
(device->instance->debug_flags & RADV_DEBUG_NO_HIZ))
|
|
|
|
surface->flags |= RADEON_SURF_NO_HTILE;
|
2020-05-02 21:01:44 +01:00
|
|
|
if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
|
|
|
|
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
if (is_stencil)
|
2017-05-10 21:33:13 +01:00
|
|
|
surface->flags |= RADEON_SURF_SBUFFER;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-12-17 08:59:49 +00:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
|
2019-09-24 15:33:39 +01:00
|
|
|
vk_format_get_blocksizebits(image_format) == 128 &&
|
|
|
|
vk_format_is_compressed(image_format))
|
2018-12-17 08:59:49 +00:00
|
|
|
surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
|
|
|
|
|
2019-09-24 15:33:39 +01:00
|
|
|
if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
|
2016-10-07 00:16:09 +01:00
|
|
|
surface->flags |= RADEON_SURF_DISABLE_DCC;
|
2018-03-30 15:46:14 +01:00
|
|
|
|
2020-05-24 10:57:09 +01:00
|
|
|
if (!radv_use_fmask_for_image(image))
|
|
|
|
surface->flags |= RADEON_SURF_NO_FMASK;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
return 0;
|
|
|
|
}
|
2017-09-22 17:21:33 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
static inline unsigned
|
2018-07-16 19:51:26 +01:00
|
|
|
si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
if (stencil)
|
2018-07-16 19:51:26 +01:00
|
|
|
return plane->surface.u.legacy.stencil_tiling_index[level];
|
2016-10-07 00:16:09 +01:00
|
|
|
else
|
2018-07-16 19:51:26 +01:00
|
|
|
return plane->surface.u.legacy.tiling_index[level];
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned radv_map_swizzle(unsigned swizzle)
|
|
|
|
{
|
|
|
|
switch (swizzle) {
|
|
|
|
case VK_SWIZZLE_Y:
|
|
|
|
return V_008F0C_SQ_SEL_Y;
|
|
|
|
case VK_SWIZZLE_Z:
|
|
|
|
return V_008F0C_SQ_SEL_Z;
|
|
|
|
case VK_SWIZZLE_W:
|
|
|
|
return V_008F0C_SQ_SEL_W;
|
|
|
|
case VK_SWIZZLE_0:
|
|
|
|
return V_008F0C_SQ_SEL_0;
|
|
|
|
case VK_SWIZZLE_1:
|
|
|
|
return V_008F0C_SQ_SEL_1;
|
|
|
|
default: /* VK_SWIZZLE_X */
|
|
|
|
return V_008F0C_SQ_SEL_X;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_make_buffer_descriptor(struct radv_device *device,
|
|
|
|
struct radv_buffer *buffer,
|
|
|
|
VkFormat vk_format,
|
|
|
|
unsigned offset,
|
|
|
|
unsigned range,
|
|
|
|
uint32_t *state)
|
|
|
|
{
|
|
|
|
const struct vk_format_description *desc;
|
|
|
|
unsigned stride;
|
2017-09-17 11:15:02 +01:00
|
|
|
uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
|
2016-10-07 00:16:09 +01:00
|
|
|
uint64_t va = gpu_address + buffer->offset;
|
|
|
|
unsigned num_format, data_format;
|
|
|
|
int first_non_void;
|
|
|
|
desc = vk_format_description(vk_format);
|
|
|
|
first_non_void = vk_format_get_first_non_void_channel(vk_format);
|
|
|
|
stride = desc->block.bits / 8;
|
|
|
|
|
|
|
|
va += offset;
|
|
|
|
state[0] = va;
|
|
|
|
state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
|
|
|
|
S_008F04_STRIDE(stride);
|
2017-07-24 11:42:54 +01:00
|
|
|
|
2019-05-15 03:16:20 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
|
2017-07-24 11:42:54 +01:00
|
|
|
range /= stride;
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
state[2] = range;
|
|
|
|
state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
|
|
|
|
S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
|
|
|
|
S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
|
2019-06-25 08:37:58 +01:00
|
|
|
S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
|
|
|
|
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX10) {
|
2020-06-02 00:44:52 +01:00
|
|
|
const struct gfx10_format *fmt = &gfx10_format_table[vk_format_to_pipe_format(vk_format)];
|
2019-06-25 08:37:58 +01:00
|
|
|
|
|
|
|
/* OOB_SELECT chooses the out-of-bounds check:
|
|
|
|
* - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
|
|
|
|
* - 1: index >= NUM_RECORDS
|
|
|
|
* - 2: NUM_RECORDS == 0
|
|
|
|
* - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
|
|
|
|
* else: swizzle_address >= NUM_RECORDS
|
|
|
|
*/
|
|
|
|
state[3] |= S_008F0C_FORMAT(fmt->img_format) |
|
2019-12-18 13:23:26 +00:00
|
|
|
S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
|
2019-06-25 08:37:58 +01:00
|
|
|
S_008F0C_RESOURCE_LEVEL(1);
|
|
|
|
} else {
|
|
|
|
num_format = radv_translate_buffer_numformat(desc, first_non_void);
|
|
|
|
data_format = radv_translate_buffer_dataformat(desc, first_non_void);
|
|
|
|
|
|
|
|
assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
|
|
|
|
assert(num_format != ~0);
|
|
|
|
|
|
|
|
state[3] |= S_008F0C_NUM_FORMAT(num_format) |
|
|
|
|
S_008F0C_DATA_FORMAT(data_format);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
si_set_mutable_tex_desc_fields(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
2017-05-10 22:01:00 +01:00
|
|
|
const struct legacy_surf_level *base_level_info,
|
2018-12-02 22:58:54 +00:00
|
|
|
unsigned plane_id,
|
2016-10-07 00:16:09 +01:00
|
|
|
unsigned base_level, unsigned first_level,
|
|
|
|
unsigned block_width, bool is_stencil,
|
2019-08-05 00:19:29 +01:00
|
|
|
bool is_storage_image, bool disable_compression,
|
|
|
|
uint32_t *state)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2018-12-02 22:58:54 +00:00
|
|
|
struct radv_image_plane *plane = &image->planes[plane_id];
|
2017-09-17 11:15:02 +01:00
|
|
|
uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
|
2018-07-16 19:51:26 +01:00
|
|
|
uint64_t va = gpu_address + plane->offset;
|
2017-06-05 23:54:38 +01:00
|
|
|
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
|
|
|
|
uint64_t meta_va = 0;
|
|
|
|
if (chip_class >= GFX9) {
|
|
|
|
if (is_stencil)
|
2018-07-16 19:51:26 +01:00
|
|
|
va += plane->surface.u.gfx9.stencil_offset;
|
2017-06-05 23:54:38 +01:00
|
|
|
else
|
2018-07-16 19:51:26 +01:00
|
|
|
va += plane->surface.u.gfx9.surf_offset;
|
2017-06-05 23:54:38 +01:00
|
|
|
} else
|
|
|
|
va += base_level_info->offset;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
state[0] = va >> 8;
|
2017-08-15 03:40:41 +01:00
|
|
|
if (chip_class >= GFX9 ||
|
|
|
|
base_level_info->mode == RADEON_SURF_MODE_2D)
|
2018-07-16 19:51:26 +01:00
|
|
|
state[0] |= plane->surface.tile_swizzle;
|
2017-06-05 23:54:38 +01:00
|
|
|
state[1] &= C_008F14_BASE_ADDRESS_HI;
|
2016-10-07 00:16:09 +01:00
|
|
|
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
|
|
|
|
|
2019-05-15 03:16:20 +01:00
|
|
|
if (chip_class >= GFX8) {
|
2017-06-05 23:54:38 +01:00
|
|
|
state[6] &= C_008F28_COMPRESSION_EN;
|
|
|
|
state[7] = 0;
|
2019-08-05 00:19:29 +01:00
|
|
|
if (!disable_compression && radv_dcc_enabled(image, first_level)) {
|
2020-05-24 12:47:20 +01:00
|
|
|
meta_va = gpu_address + plane->surface.dcc_offset;
|
2019-05-15 03:16:20 +01:00
|
|
|
if (chip_class <= GFX8)
|
2017-06-05 23:54:38 +01:00
|
|
|
meta_va += base_level_info->dcc_offset;
|
2019-08-01 14:45:10 +01:00
|
|
|
|
2019-08-01 14:45:11 +01:00
|
|
|
unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
|
|
|
|
dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
|
|
|
|
meta_va |= dcc_tile_swizzle;
|
2019-08-05 00:19:29 +01:00
|
|
|
} else if (!disable_compression &&
|
2018-04-06 15:17:26 +01:00
|
|
|
radv_image_is_tc_compat_htile(image)) {
|
2020-05-24 12:47:20 +01:00
|
|
|
meta_va = gpu_address + plane->surface.htile_offset;
|
2017-05-09 07:26:07 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (meta_va) {
|
2017-06-05 23:54:38 +01:00
|
|
|
state[6] |= S_008F28_COMPRESSION_EN(1);
|
2019-08-01 14:45:10 +01:00
|
|
|
if (chip_class <= GFX9)
|
2019-06-25 08:29:19 +01:00
|
|
|
state[7] = meta_va >> 8;
|
2017-06-05 23:54:38 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-06-25 08:29:19 +01:00
|
|
|
if (chip_class >= GFX10) {
|
|
|
|
state[3] &= C_00A00C_SW_MODE;
|
|
|
|
|
|
|
|
if (is_stencil) {
|
|
|
|
state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
|
|
|
|
} else {
|
|
|
|
state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
state[6] &= C_00A018_META_DATA_ADDRESS_LO &
|
|
|
|
C_00A018_META_PIPE_ALIGNED;
|
|
|
|
|
|
|
|
if (meta_va) {
|
2020-05-02 14:19:18 +01:00
|
|
|
struct gfx9_surf_meta_flags meta = {
|
|
|
|
.rb_aligned = 1,
|
|
|
|
.pipe_aligned = 1,
|
|
|
|
};
|
2019-06-25 08:29:19 +01:00
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
if (plane->surface.dcc_offset)
|
2019-06-25 08:29:19 +01:00
|
|
|
meta = plane->surface.u.gfx9.dcc;
|
|
|
|
|
|
|
|
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
|
|
|
|
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
state[7] = meta_va >> 16;
|
2019-07-18 14:51:28 +01:00
|
|
|
} else if (chip_class == GFX9) {
|
2017-06-05 23:54:38 +01:00
|
|
|
state[3] &= C_008F1C_SW_MODE;
|
2019-05-07 00:44:52 +01:00
|
|
|
state[4] &= C_008F20_PITCH;
|
2017-06-05 23:54:38 +01:00
|
|
|
|
|
|
|
if (is_stencil) {
|
2018-07-16 19:51:26 +01:00
|
|
|
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
|
2019-05-07 00:44:52 +01:00
|
|
|
state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
|
2017-06-05 23:54:38 +01:00
|
|
|
} else {
|
2018-07-16 19:51:26 +01:00
|
|
|
state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
|
2019-05-07 00:44:52 +01:00
|
|
|
state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
|
2017-06-05 23:54:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
state[5] &= C_008F24_META_DATA_ADDRESS &
|
|
|
|
C_008F24_META_PIPE_ALIGNED &
|
|
|
|
C_008F24_META_RB_ALIGNED;
|
|
|
|
if (meta_va) {
|
2020-05-02 14:19:18 +01:00
|
|
|
struct gfx9_surf_meta_flags meta = {
|
|
|
|
.rb_aligned = 1,
|
|
|
|
.pipe_aligned = 1,
|
|
|
|
};
|
2017-06-05 23:54:38 +01:00
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
if (plane->surface.dcc_offset)
|
2018-07-16 19:51:26 +01:00
|
|
|
meta = plane->surface.u.gfx9.dcc;
|
2017-06-05 23:54:38 +01:00
|
|
|
|
|
|
|
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
|
|
|
|
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
|
|
|
|
S_008F24_META_RB_ALIGNED(meta.rb_aligned);
|
|
|
|
}
|
|
|
|
} else {
|
2019-05-15 03:16:20 +01:00
|
|
|
/* GFX6-GFX8 */
|
2017-06-05 23:54:38 +01:00
|
|
|
unsigned pitch = base_level_info->nblk_x * block_width;
|
2018-07-16 19:51:26 +01:00
|
|
|
unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
|
2017-06-05 23:54:38 +01:00
|
|
|
|
|
|
|
state[3] &= C_008F1C_TILING_INDEX;
|
|
|
|
state[3] |= S_008F1C_TILING_INDEX(index);
|
2019-05-07 00:44:52 +01:00
|
|
|
state[4] &= C_008F20_PITCH;
|
|
|
|
state[4] |= S_008F20_PITCH(pitch - 1);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
|
2017-08-16 06:20:29 +01:00
|
|
|
unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
|
|
|
|
return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
|
2017-08-16 06:20:29 +01:00
|
|
|
|
|
|
|
/* GFX9 allocates 1D textures as 2D. */
|
|
|
|
if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
|
|
|
|
image_type = VK_IMAGE_TYPE_2D;
|
2016-10-07 00:16:09 +01:00
|
|
|
switch (image_type) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
if (nr_samples > 1)
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
|
|
|
|
else
|
|
|
|
return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
if (view_type == VK_IMAGE_VIEW_TYPE_3D)
|
|
|
|
return V_008F1C_SQ_RSRC_IMG_3D;
|
|
|
|
else
|
|
|
|
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
|
|
|
|
default:
|
2018-05-09 22:26:21 +01:00
|
|
|
unreachable("illegal image type");
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
}
|
2017-06-05 23:54:38 +01:00
|
|
|
|
2017-12-29 01:32:36 +00:00
|
|
|
static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
|
2017-06-05 23:54:38 +01:00
|
|
|
{
|
|
|
|
unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
|
|
|
|
|
|
|
|
if (swizzle[3] == VK_SWIZZLE_X) {
|
|
|
|
/* For the pre-defined border color values (white, opaque
|
|
|
|
* black, transparent black), the only thing that matters is
|
|
|
|
* that the alpha channel winds up in the correct place
|
|
|
|
* (because the RGB channels are all the same) so either of
|
|
|
|
* these enumerations will work.
|
|
|
|
*/
|
|
|
|
if (swizzle[2] == VK_SWIZZLE_Y)
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
|
|
|
|
else
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
|
|
|
|
} else if (swizzle[0] == VK_SWIZZLE_X) {
|
|
|
|
if (swizzle[1] == VK_SWIZZLE_Y)
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
|
|
|
|
else
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
|
|
|
|
} else if (swizzle[1] == VK_SWIZZLE_X) {
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
|
|
|
|
} else if (swizzle[2] == VK_SWIZZLE_X) {
|
|
|
|
bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
|
|
|
|
}
|
|
|
|
|
|
|
|
return bc_swizzle;
|
|
|
|
}
|
|
|
|
|
2019-10-11 16:40:59 +01:00
|
|
|
bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
|
2019-07-24 15:50:38 +01:00
|
|
|
{
|
|
|
|
const struct vk_format_description *desc = vk_format_description(format);
|
|
|
|
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1)
|
|
|
|
return desc->swizzle[3] == VK_SWIZZLE_X;
|
|
|
|
|
|
|
|
return radv_translate_colorswap(format, false) <= 1;
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
/**
|
2019-06-25 08:23:04 +01:00
|
|
|
* Build the sampler view descriptor for a texture (GFX10).
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
gfx10_make_texture_descriptor(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
bool is_storage_image,
|
|
|
|
VkImageViewType view_type,
|
|
|
|
VkFormat vk_format,
|
|
|
|
const VkComponentMapping *mapping,
|
|
|
|
unsigned first_level, unsigned last_level,
|
|
|
|
unsigned first_layer, unsigned last_layer,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
uint32_t *state,
|
|
|
|
uint32_t *fmask_state)
|
|
|
|
{
|
|
|
|
const struct vk_format_description *desc;
|
|
|
|
enum vk_swizzle swizzle[4];
|
|
|
|
unsigned img_format;
|
|
|
|
unsigned type;
|
|
|
|
|
|
|
|
desc = vk_format_description(vk_format);
|
2020-06-02 00:44:52 +01:00
|
|
|
img_format = gfx10_format_table[vk_format_to_pipe_format(vk_format)].img_format;
|
2019-06-25 08:23:04 +01:00
|
|
|
|
|
|
|
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
|
|
|
|
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
|
|
|
|
vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
|
|
|
|
} else {
|
|
|
|
vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
|
|
|
|
}
|
|
|
|
|
|
|
|
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
|
2019-07-12 07:17:09 +01:00
|
|
|
is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
|
2019-06-25 08:23:04 +01:00
|
|
|
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
|
|
|
|
height = 1;
|
|
|
|
depth = image->info.array_size;
|
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
|
|
|
|
type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
|
|
|
|
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
|
|
|
|
depth = image->info.array_size;
|
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
|
|
|
|
depth = image->info.array_size / 6;
|
|
|
|
|
|
|
|
state[0] = 0;
|
|
|
|
state[1] = S_00A004_FORMAT(img_format) |
|
|
|
|
S_00A004_WIDTH_LO(width - 1);
|
|
|
|
state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
|
|
|
|
S_00A008_HEIGHT(height - 1) |
|
|
|
|
S_00A008_RESOURCE_LEVEL(1);
|
|
|
|
state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
|
|
|
|
S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
|
|
|
|
S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
|
|
|
|
S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
|
|
|
|
S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
|
|
|
|
0 : first_level) |
|
|
|
|
S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
|
|
|
last_level) |
|
|
|
|
S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
|
|
|
|
S_00A00C_TYPE(type);
|
|
|
|
/* Depth is the the last accessible layer on gfx9+. The hw doesn't need
|
|
|
|
* to know the total number of layers.
|
|
|
|
*/
|
|
|
|
state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
|
|
|
|
S_00A010_BASE_ARRAY(first_layer);
|
2019-10-21 14:11:35 +01:00
|
|
|
state[5] = S_00A014_ARRAY_PITCH(0) |
|
2019-06-25 08:23:04 +01:00
|
|
|
S_00A014_MAX_MIP(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
|
|
|
image->info.levels - 1) |
|
|
|
|
S_00A014_PERF_MOD(4);
|
|
|
|
state[6] = 0;
|
|
|
|
state[7] = 0;
|
|
|
|
|
|
|
|
if (radv_dcc_enabled(image, first_level)) {
|
|
|
|
state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
|
|
|
|
S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
|
2019-07-24 15:50:38 +01:00
|
|
|
S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
|
2019-06-25 08:23:04 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize the sampler view for FMASK. */
|
|
|
|
if (radv_image_has_fmask(image)) {
|
|
|
|
uint64_t gpu_address = radv_buffer_get_va(image->bo);
|
|
|
|
uint32_t format;
|
|
|
|
uint64_t va;
|
|
|
|
|
|
|
|
assert(image->plane_count == 1);
|
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
|
2019-06-25 08:23:04 +01:00
|
|
|
|
|
|
|
switch (image->info.samples) {
|
|
|
|
case 2:
|
|
|
|
format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("invalid nr_samples");
|
|
|
|
}
|
|
|
|
|
|
|
|
fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
|
|
|
|
fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
|
|
|
|
S_00A004_FORMAT(format) |
|
|
|
|
S_00A004_WIDTH_LO(width - 1);
|
|
|
|
fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
|
|
|
|
S_00A008_HEIGHT(height - 1) |
|
|
|
|
S_00A008_RESOURCE_LEVEL(1);
|
|
|
|
fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
|
|
|
|
S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
|
|
|
|
fmask_state[4] = S_00A010_DEPTH(last_layer) |
|
|
|
|
S_00A010_BASE_ARRAY(first_layer);
|
|
|
|
fmask_state[5] = 0;
|
2020-05-02 14:19:18 +01:00
|
|
|
fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
|
2019-06-25 08:23:04 +01:00
|
|
|
fmask_state[7] = 0;
|
|
|
|
} else if (fmask_state)
|
|
|
|
memset(fmask_state, 0, 8 * 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Build the sampler view descriptor for a texture (SI-GFX9)
|
2016-10-07 00:16:09 +01:00
|
|
|
*/
|
|
|
|
static void
|
|
|
|
si_make_texture_descriptor(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
2017-07-12 10:29:52 +01:00
|
|
|
bool is_storage_image,
|
2016-10-07 00:16:09 +01:00
|
|
|
VkImageViewType view_type,
|
|
|
|
VkFormat vk_format,
|
|
|
|
const VkComponentMapping *mapping,
|
|
|
|
unsigned first_level, unsigned last_level,
|
|
|
|
unsigned first_layer, unsigned last_layer,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
uint32_t *state,
|
|
|
|
uint32_t *fmask_state)
|
|
|
|
{
|
|
|
|
const struct vk_format_description *desc;
|
|
|
|
enum vk_swizzle swizzle[4];
|
|
|
|
int first_non_void;
|
|
|
|
unsigned num_format, data_format, type;
|
|
|
|
|
|
|
|
desc = vk_format_description(vk_format);
|
|
|
|
|
|
|
|
if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
|
|
|
|
const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
|
2016-11-15 06:46:50 +00:00
|
|
|
vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
|
2016-10-07 00:16:09 +01:00
|
|
|
} else {
|
|
|
|
vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
|
|
|
|
}
|
|
|
|
|
|
|
|
first_non_void = vk_format_get_first_non_void_channel(vk_format);
|
|
|
|
|
|
|
|
num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
|
|
|
|
if (num_format == ~0) {
|
|
|
|
num_format = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
|
|
|
|
if (data_format == ~0) {
|
|
|
|
data_format = 0;
|
|
|
|
}
|
|
|
|
|
2017-12-27 01:22:58 +00:00
|
|
|
/* S8 with either Z16 or Z32 HTILE need a special format. */
|
2019-07-18 14:51:28 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class == GFX9 &&
|
2017-12-07 10:39:46 +00:00
|
|
|
vk_format == VK_FORMAT_S8_UINT &&
|
2018-04-06 15:17:26 +01:00
|
|
|
radv_image_is_tc_compat_htile(image)) {
|
2017-12-27 01:22:58 +00:00
|
|
|
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
|
|
|
|
data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
|
|
|
|
else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
|
|
|
|
data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
|
|
|
|
}
|
2017-05-02 00:49:14 +01:00
|
|
|
type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
|
2019-07-12 07:17:09 +01:00
|
|
|
is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
|
2016-10-07 00:16:09 +01:00
|
|
|
if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
|
|
|
|
height = 1;
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
|
|
|
|
type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
|
|
|
|
if (view_type != VK_IMAGE_VIEW_TYPE_3D)
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
} else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
|
2017-05-02 00:49:14 +01:00
|
|
|
depth = image->info.array_size / 6;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
state[0] = 0;
|
2017-11-13 15:35:59 +00:00
|
|
|
state[1] = (S_008F14_DATA_FORMAT(data_format) |
|
|
|
|
S_008F14_NUM_FORMAT(num_format));
|
2016-10-07 00:16:09 +01:00
|
|
|
state[2] = (S_008F18_WIDTH(width - 1) |
|
2017-04-28 07:17:10 +01:00
|
|
|
S_008F18_HEIGHT(height - 1) |
|
|
|
|
S_008F18_PERF_MOD(4));
|
2016-10-07 00:16:09 +01:00
|
|
|
state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
|
|
|
|
S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
|
|
|
|
S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
|
|
|
|
S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
|
2017-05-02 00:49:14 +01:00
|
|
|
S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
|
2016-10-07 00:16:09 +01:00
|
|
|
0 : first_level) |
|
2017-05-02 00:49:14 +01:00
|
|
|
S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
2016-10-07 00:16:09 +01:00
|
|
|
last_level) |
|
|
|
|
S_008F1C_TYPE(type));
|
2017-06-05 02:09:30 +01:00
|
|
|
state[4] = 0;
|
|
|
|
state[5] = S_008F24_BASE_ARRAY(first_layer);
|
2016-10-07 00:16:09 +01:00
|
|
|
state[6] = 0;
|
|
|
|
state[7] = 0;
|
|
|
|
|
2019-07-18 14:51:28 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class == GFX9) {
|
2017-12-29 01:32:36 +00:00
|
|
|
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
|
2017-06-05 23:54:38 +01:00
|
|
|
|
2018-05-09 22:26:21 +01:00
|
|
|
/* Depth is the last accessible layer on Gfx9.
|
2017-06-05 23:54:38 +01:00
|
|
|
* The hw doesn't need to know the total number of layers.
|
|
|
|
*/
|
|
|
|
if (type == V_008F1C_SQ_RSRC_IMG_3D)
|
|
|
|
state[4] |= S_008F20_DEPTH(depth - 1);
|
|
|
|
else
|
|
|
|
state[4] |= S_008F20_DEPTH(last_layer);
|
|
|
|
|
|
|
|
state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
|
|
|
|
state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
|
|
|
|
util_logbase2(image->info.samples) :
|
2017-08-21 08:27:25 +01:00
|
|
|
image->info.levels - 1);
|
2017-06-05 23:54:38 +01:00
|
|
|
} else {
|
2017-06-05 02:09:30 +01:00
|
|
|
state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
|
|
|
|
state[4] |= S_008F20_DEPTH(depth - 1);
|
|
|
|
state[5] |= S_008F24_LAST_ARRAY(last_layer);
|
|
|
|
}
|
2020-05-24 12:47:20 +01:00
|
|
|
if (image->planes[0].surface.dcc_offset) {
|
2019-07-24 15:50:38 +01:00
|
|
|
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
|
2016-10-07 00:16:09 +01:00
|
|
|
} else {
|
|
|
|
/* The last dword is unused by hw. The shader uses it to clear
|
|
|
|
* bits in the first dword of sampler state.
|
|
|
|
*/
|
2019-05-15 03:16:20 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
|
2016-10-07 00:16:09 +01:00
|
|
|
if (first_level == last_level)
|
|
|
|
state[7] = C_008F30_MAX_ANISO_RATIO;
|
|
|
|
else
|
|
|
|
state[7] = 0xffffffff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize the sampler view for FMASK. */
|
2018-04-06 14:37:28 +01:00
|
|
|
if (radv_image_has_fmask(image)) {
|
2017-06-05 23:54:38 +01:00
|
|
|
uint32_t fmask_format, num_format;
|
2017-09-17 11:15:02 +01:00
|
|
|
uint64_t gpu_address = radv_buffer_get_va(image->bo);
|
2016-10-07 00:16:09 +01:00
|
|
|
uint64_t va;
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
assert(image->plane_count == 1);
|
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
va = gpu_address + image->offset + image->planes[0].surface.fmask_offset;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2019-07-18 14:51:28 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class == GFX9) {
|
2017-06-05 23:54:38 +01:00
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
|
|
|
|
switch (image->info.samples) {
|
|
|
|
case 2:
|
|
|
|
num_format = V_008F14_IMG_FMASK_8_2_2;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
num_format = V_008F14_IMG_FMASK_8_4_4;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
num_format = V_008F14_IMG_FMASK_32_8_8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("invalid nr_samples");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (image->info.samples) {
|
|
|
|
case 2:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
|
|
|
|
}
|
|
|
|
num_format = V_008F14_IMG_NUM_FORMAT_UINT;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
fmask_state[0] = va >> 8;
|
2019-08-01 16:59:56 +01:00
|
|
|
fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
|
2017-11-13 15:35:59 +00:00
|
|
|
S_008F14_DATA_FORMAT(fmask_format) |
|
|
|
|
S_008F14_NUM_FORMAT(num_format);
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[2] = S_008F18_WIDTH(width - 1) |
|
|
|
|
S_008F18_HEIGHT(height - 1);
|
|
|
|
fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
|
|
|
|
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
|
2018-03-19 07:13:46 +00:00
|
|
|
S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
|
2017-06-05 02:09:30 +01:00
|
|
|
fmask_state[4] = 0;
|
|
|
|
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
|
2016-10-07 00:16:09 +01:00
|
|
|
fmask_state[6] = 0;
|
|
|
|
fmask_state[7] = 0;
|
2017-06-05 02:09:30 +01:00
|
|
|
|
2019-07-18 14:51:28 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class == GFX9) {
|
2018-07-16 19:51:26 +01:00
|
|
|
fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
|
2017-06-05 23:54:38 +01:00
|
|
|
fmask_state[4] |= S_008F20_DEPTH(last_layer) |
|
2019-05-07 00:44:52 +01:00
|
|
|
S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
|
2020-05-02 14:19:18 +01:00
|
|
|
fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
|
|
|
|
S_008F24_META_RB_ALIGNED(1);
|
2018-11-14 15:24:02 +00:00
|
|
|
|
|
|
|
if (radv_image_is_tc_compat_cmask(image)) {
|
2020-05-24 12:47:20 +01:00
|
|
|
va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
|
2018-11-14 15:24:02 +00:00
|
|
|
|
|
|
|
fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
|
|
|
|
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
|
|
|
|
fmask_state[7] |= va >> 8;
|
|
|
|
}
|
2017-06-05 23:54:38 +01:00
|
|
|
} else {
|
2019-08-01 16:59:56 +01:00
|
|
|
fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
|
2017-06-05 02:09:30 +01:00
|
|
|
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
|
2019-08-01 16:59:56 +01:00
|
|
|
S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
|
2017-06-05 02:09:30 +01:00
|
|
|
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
|
2018-11-14 15:24:02 +00:00
|
|
|
|
|
|
|
if (radv_image_is_tc_compat_cmask(image)) {
|
2020-05-24 12:47:20 +01:00
|
|
|
va = gpu_address + image->offset + image->planes[0].surface.cmask_offset;
|
2018-11-14 15:24:02 +00:00
|
|
|
|
|
|
|
fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
|
|
|
|
fmask_state[7] |= va >> 8;
|
|
|
|
}
|
2017-06-05 02:09:30 +01:00
|
|
|
}
|
2017-06-09 02:11:29 +01:00
|
|
|
} else if (fmask_state)
|
|
|
|
memset(fmask_state, 0, 8 * 4);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2019-06-25 08:23:04 +01:00
|
|
|
static void
|
|
|
|
radv_make_texture_descriptor(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
bool is_storage_image,
|
|
|
|
VkImageViewType view_type,
|
|
|
|
VkFormat vk_format,
|
|
|
|
const VkComponentMapping *mapping,
|
|
|
|
unsigned first_level, unsigned last_level,
|
|
|
|
unsigned first_layer, unsigned last_layer,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
uint32_t *state,
|
|
|
|
uint32_t *fmask_state)
|
|
|
|
{
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX10) {
|
|
|
|
gfx10_make_texture_descriptor(device, image, is_storage_image,
|
|
|
|
view_type, vk_format, mapping,
|
|
|
|
first_level, last_level,
|
|
|
|
first_layer, last_layer,
|
|
|
|
width, height, depth,
|
|
|
|
state, fmask_state);
|
|
|
|
} else {
|
|
|
|
si_make_texture_descriptor(device, image, is_storage_image,
|
|
|
|
view_type, vk_format, mapping,
|
|
|
|
first_level, last_level,
|
|
|
|
first_layer, last_layer,
|
|
|
|
width, height, depth,
|
|
|
|
state, fmask_state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
static void
|
|
|
|
radv_query_opaque_metadata(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radeon_bo_metadata *md)
|
|
|
|
{
|
|
|
|
static const VkComponentMapping fixedmapping;
|
|
|
|
uint32_t desc[8], i;
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
assert(image->plane_count == 1);
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
/* Metadata image format format version 1:
|
|
|
|
* [0] = 1 (metadata format identifier)
|
|
|
|
* [1] = (VENDOR_ID << 16) | PCI_ID
|
|
|
|
* [2:9] = image descriptor for the whole resource
|
|
|
|
* [2] is always 0, because the base address is cleared
|
|
|
|
* [9] is the DCC offset bits [39:8] from the beginning of
|
|
|
|
* the buffer
|
|
|
|
* [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
|
|
|
|
*/
|
|
|
|
md->metadata[0] = 1; /* metadata image format version 1 */
|
|
|
|
|
|
|
|
/* TILE_MODE_INDEX is ambiguous without a PCI ID. */
|
|
|
|
md->metadata[1] = si_get_bo_metadata_word1(device);
|
|
|
|
|
|
|
|
|
2019-06-25 08:23:04 +01:00
|
|
|
radv_make_texture_descriptor(device, image, false,
|
|
|
|
(VkImageViewType)image->type, image->vk_format,
|
|
|
|
&fixedmapping, 0, image->info.levels - 1, 0,
|
|
|
|
image->info.array_size - 1,
|
|
|
|
image->info.width, image->info.height,
|
|
|
|
image->info.depth,
|
|
|
|
desc, NULL);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-12-02 22:58:54 +00:00
|
|
|
si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
|
2019-08-05 00:19:29 +01:00
|
|
|
image->planes[0].surface.blk_w, false, false, false, desc);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
/* Clear the base address and set the relative DCC offset. */
|
|
|
|
desc[0] = 0;
|
|
|
|
desc[1] &= C_008F14_BASE_ADDRESS_HI;
|
2020-05-24 12:47:20 +01:00
|
|
|
desc[7] = image->planes[0].surface.dcc_offset >> 8;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
/* Dwords [2:9] contain the image descriptor. */
|
|
|
|
memcpy(&md->metadata[2], desc, sizeof(desc));
|
|
|
|
|
|
|
|
/* Dwords [10:..] contain the mipmap level offsets. */
|
2019-05-15 03:16:20 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class <= GFX8) {
|
2017-08-15 05:02:54 +01:00
|
|
|
for (i = 0; i <= image->info.levels - 1; i++)
|
2018-07-16 19:51:26 +01:00
|
|
|
md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
|
2017-08-15 05:02:54 +01:00
|
|
|
md->size_metadata = (11 + image->info.levels - 1) * 4;
|
2019-07-25 15:53:34 +01:00
|
|
|
} else
|
|
|
|
md->size_metadata = 10 * 4;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_init_metadata(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radeon_bo_metadata *metadata)
|
|
|
|
{
|
2018-07-16 19:51:26 +01:00
|
|
|
struct radeon_surf *surface = &image->planes[0].surface;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
memset(metadata, 0, sizeof(*metadata));
|
|
|
|
|
2017-05-24 02:37:06 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
|
2019-12-31 20:19:20 +00:00
|
|
|
metadata->u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
|
2017-05-24 02:37:06 +01:00
|
|
|
} else {
|
|
|
|
metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
|
|
|
|
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
|
|
|
|
metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
|
|
|
|
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
|
|
|
|
metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
|
|
|
|
metadata->u.legacy.bankw = surface->u.legacy.bankw;
|
|
|
|
metadata->u.legacy.bankh = surface->u.legacy.bankh;
|
|
|
|
metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
|
|
|
|
metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
|
|
|
|
metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
|
|
|
|
metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
|
|
|
|
metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_query_opaque_metadata(device, image, metadata);
|
|
|
|
}
|
|
|
|
|
2019-05-06 14:44:04 +01:00
|
|
|
void
|
|
|
|
radv_image_override_offset_stride(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
uint64_t offset, uint32_t stride)
|
|
|
|
{
|
2020-05-04 12:43:44 +01:00
|
|
|
ac_surface_override_offset_stride(&device->physical_device->rad_info,
|
|
|
|
&image->planes[0].surface,
|
|
|
|
image->info.levels, offset, stride);
|
2019-05-06 14:44:04 +01:00
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
static void
|
|
|
|
radv_image_alloc_fmask(struct radv_device *device,
|
|
|
|
struct radv_image *image)
|
|
|
|
{
|
2019-08-01 16:59:56 +01:00
|
|
|
unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
image->planes[0].surface.fmask_offset = align64(image->size, fmask_alignment);
|
|
|
|
image->size = image->planes[0].surface.fmask_offset + image->planes[0].surface.fmask_size;
|
2019-08-01 16:59:56 +01:00
|
|
|
image->alignment = MAX2(image->alignment, fmask_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_image_alloc_cmask(struct radv_device *device,
|
|
|
|
struct radv_image *image)
|
|
|
|
{
|
2019-08-01 16:59:55 +01:00
|
|
|
unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
|
|
|
|
unsigned cmask_size = image->planes[0].surface.cmask_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2019-08-01 16:59:55 +01:00
|
|
|
if (!cmask_size)
|
2019-07-07 20:24:17 +01:00
|
|
|
return;
|
|
|
|
|
2019-08-01 16:59:55 +01:00
|
|
|
assert(cmask_alignment);
|
2019-07-07 20:24:17 +01:00
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
image->planes[0].surface.cmask_offset = align64(image->size, cmask_alignment);
|
2020-05-24 13:14:34 +01:00
|
|
|
image->size = image->planes[0].surface.cmask_offset + cmask_size;
|
2019-08-01 16:59:55 +01:00
|
|
|
image->alignment = MAX2(image->alignment, cmask_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2017-09-29 15:48:07 +01:00
|
|
|
radv_image_alloc_dcc(struct radv_image *image)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2018-07-16 19:51:26 +01:00
|
|
|
assert(image->plane_count == 1);
|
|
|
|
|
2020-05-24 12:47:20 +01:00
|
|
|
image->planes[0].surface.dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
|
2020-05-24 13:14:34 +01:00
|
|
|
image->size = image->planes[0].surface.dcc_offset + image->planes[0].surface.dcc_size;
|
2018-07-16 19:51:26 +01:00
|
|
|
image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2019-07-16 16:35:00 +01:00
|
|
|
radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2020-05-24 12:47:20 +01:00
|
|
|
image->planes[0].surface.htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-05-24 13:14:34 +01:00
|
|
|
image->size = image->clear_value_offset;
|
|
|
|
image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_image_alloc_values(const struct radv_device *device, struct radv_image *image)
|
|
|
|
{
|
|
|
|
if (radv_image_has_dcc(image)) {
|
|
|
|
image->fce_pred_offset = image->size;
|
|
|
|
image->size += 8 * image->info.levels;
|
|
|
|
|
|
|
|
image->dcc_pred_offset = image->size;
|
|
|
|
image->size += 8 * image->info.levels;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (radv_image_has_dcc(image) || radv_image_has_cmask(image) ||
|
|
|
|
radv_image_has_htile(image)) {
|
|
|
|
image->clear_value_offset = image->size;
|
|
|
|
image->size += 8 * image->info.levels;
|
|
|
|
}
|
|
|
|
|
2019-07-16 16:35:00 +01:00
|
|
|
if (radv_image_is_tc_compat_htile(image) &&
|
2019-08-21 10:21:05 +01:00
|
|
|
device->physical_device->rad_info.has_tc_compat_zrange_bug) {
|
2018-12-03 21:45:03 +00:00
|
|
|
/* Metadata for the TC-compatible HTILE hardware bug which
|
|
|
|
* have to be fixed by updating ZRANGE_PRECISION when doing
|
|
|
|
* fast depth clears to 0.0f.
|
|
|
|
*/
|
2019-07-02 13:50:28 +01:00
|
|
|
image->tc_compat_zrange_offset = image->size;
|
2020-05-24 13:14:34 +01:00
|
|
|
image->size += image->info.levels * 4;
|
2018-12-03 21:45:03 +00:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2017-09-29 15:48:07 +01:00
|
|
|
static inline bool
|
|
|
|
radv_image_can_enable_cmask(struct radv_image *image)
|
|
|
|
{
|
2018-07-16 19:51:26 +01:00
|
|
|
if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
|
2017-10-12 21:55:32 +01:00
|
|
|
/* Do not enable CMASK for non-MSAA images (fast color clear)
|
|
|
|
* because 128 bit formats are not supported, but FMASK might
|
|
|
|
* still be used.
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-05-24 12:57:02 +01:00
|
|
|
return radv_image_use_fast_clear_for_image(image) &&
|
2017-09-29 15:48:07 +01:00
|
|
|
image->info.levels == 1 &&
|
2020-05-24 12:25:53 +01:00
|
|
|
image->info.depth == 1;
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
static void radv_image_disable_dcc(struct radv_image *image)
|
|
|
|
{
|
|
|
|
for (unsigned i = 0; i < image->plane_count; ++i)
|
|
|
|
image->planes[i].surface.dcc_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void radv_image_disable_htile(struct radv_image *image)
|
|
|
|
{
|
|
|
|
for (unsigned i = 0; i < image->plane_count; ++i)
|
|
|
|
image->planes[i].surface.htile_size = 0;
|
|
|
|
}
|
|
|
|
|
2019-09-24 18:42:49 +01:00
|
|
|
VkResult
|
2019-09-23 15:14:50 +01:00
|
|
|
radv_image_create_layout(struct radv_device *device,
|
2019-09-24 12:42:31 +01:00
|
|
|
struct radv_image_create_info create_info,
|
2019-09-23 15:14:50 +01:00
|
|
|
struct radv_image *image)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2019-09-23 15:14:50 +01:00
|
|
|
/* Check that we did not initialize things earlier */
|
|
|
|
assert(!image->planes[0].surface.surf_size);
|
2016-12-17 20:25:32 +00:00
|
|
|
|
2019-09-24 12:42:31 +01:00
|
|
|
/* Clear the pCreateInfo pointer so we catch issues in the delayed case when we test in the
|
|
|
|
* common internal case. */
|
|
|
|
create_info.vk_info = NULL;
|
|
|
|
|
2019-09-24 12:23:36 +01:00
|
|
|
struct ac_surf_info image_info = image->info;
|
2019-09-24 12:42:31 +01:00
|
|
|
VkResult result = radv_patch_image_from_extra_info(device, image, &create_info, &image_info);
|
2019-09-24 12:23:36 +01:00
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
2019-09-23 15:42:39 +01:00
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
image->size = 0;
|
|
|
|
image->alignment = 1;
|
2019-09-23 15:14:50 +01:00
|
|
|
for (unsigned plane = 0; plane < image->plane_count; ++plane) {
|
2019-09-24 12:23:36 +01:00
|
|
|
struct ac_surf_info info = image_info;
|
2018-07-16 19:51:26 +01:00
|
|
|
|
|
|
|
if (plane) {
|
2019-09-23 15:14:50 +01:00
|
|
|
const struct vk_format_description *desc = vk_format_description(image->vk_format);
|
2018-07-16 19:51:26 +01:00
|
|
|
assert(info.width % desc->width_divisor == 0);
|
|
|
|
assert(info.height % desc->height_divisor == 0);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
info.width /= desc->width_divisor;
|
|
|
|
info.height /= desc->height_divisor;
|
|
|
|
}
|
|
|
|
|
2020-05-24 11:10:00 +01:00
|
|
|
if (create_info.no_metadata_planes || image->plane_count > 1) {
|
|
|
|
image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC |
|
|
|
|
RADEON_SURF_NO_FMASK |
|
|
|
|
RADEON_SURF_NO_HTILE;
|
|
|
|
}
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
|
|
|
|
image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
|
|
|
|
image->alignment = image->planes[plane].surface.surf_alignment;
|
|
|
|
|
|
|
|
image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-05-24 11:10:00 +01:00
|
|
|
/* Try to enable DCC first. */
|
2020-05-24 12:57:02 +01:00
|
|
|
if (radv_image_has_dcc(image)) {
|
2020-05-24 11:10:00 +01:00
|
|
|
radv_image_alloc_dcc(image);
|
|
|
|
if (image->info.samples > 1) {
|
|
|
|
/* CMASK should be enabled because DCC fast
|
|
|
|
* clear with MSAA needs it.
|
|
|
|
*/
|
|
|
|
assert(radv_image_can_enable_cmask(image));
|
|
|
|
radv_image_alloc_cmask(device, image);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* When DCC cannot be enabled, try CMASK. */
|
|
|
|
radv_image_disable_dcc(image);
|
|
|
|
if (radv_image_can_enable_cmask(image)) {
|
|
|
|
radv_image_alloc_cmask(device, image);
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
2020-05-24 11:10:00 +01:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-05-24 11:10:00 +01:00
|
|
|
/* Try to enable FMASK for multisampled images. */
|
|
|
|
if (image->planes[0].surface.fmask_size) {
|
|
|
|
radv_image_alloc_fmask(device, image);
|
2018-11-14 15:24:02 +00:00
|
|
|
|
2020-05-24 11:10:00 +01:00
|
|
|
if (radv_use_tc_compat_cmask_for_image(device, image))
|
|
|
|
image->tc_compatible_cmask = true;
|
|
|
|
} else {
|
|
|
|
/* Otherwise, try to enable HTILE for depth surfaces. */
|
2020-05-24 13:00:05 +01:00
|
|
|
if (radv_image_has_htile(image)) {
|
2020-05-24 11:10:00 +01:00
|
|
|
image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
|
|
|
|
radv_image_alloc_htile(device, image);
|
2017-09-29 15:48:07 +01:00
|
|
|
} else {
|
2020-05-24 11:10:00 +01:00
|
|
|
radv_image_disable_htile(image);
|
2017-09-29 15:48:07 +01:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2020-05-24 13:14:34 +01:00
|
|
|
radv_image_alloc_values(device, image);
|
|
|
|
|
2019-09-23 15:14:50 +01:00
|
|
|
assert(image->planes[0].surface.surf_size);
|
2019-09-24 12:23:36 +01:00
|
|
|
return VK_SUCCESS;
|
2019-09-23 15:14:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_image_create(VkDevice _device,
|
|
|
|
const struct radv_image_create_info *create_info,
|
|
|
|
const VkAllocationCallbacks* alloc,
|
|
|
|
VkImage *pImage)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
|
|
|
|
struct radv_image *image = NULL;
|
2019-09-24 15:33:39 +01:00
|
|
|
VkFormat format = radv_select_android_external_format(pCreateInfo->pNext,
|
|
|
|
pCreateInfo->format);
|
2019-09-23 15:14:50 +01:00
|
|
|
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
|
|
|
|
|
2019-09-24 15:33:39 +01:00
|
|
|
const unsigned plane_count = vk_format_get_plane_count(format);
|
2019-09-23 15:14:50 +01:00
|
|
|
const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
|
|
|
|
|
|
|
|
radv_assert(pCreateInfo->mipLevels > 0);
|
|
|
|
radv_assert(pCreateInfo->arrayLayers > 0);
|
|
|
|
radv_assert(pCreateInfo->samples > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.width > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.height > 0);
|
|
|
|
radv_assert(pCreateInfo->extent.depth > 0);
|
|
|
|
|
2020-04-29 09:16:32 +01:00
|
|
|
image = vk_zalloc2(&device->vk.alloc, alloc, image_struct_size, 8,
|
2019-09-23 15:14:50 +01:00
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (!image)
|
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
|
2020-04-29 13:57:20 +01:00
|
|
|
vk_object_base_init(&device->vk, &image->base, VK_OBJECT_TYPE_IMAGE);
|
|
|
|
|
2019-09-23 15:14:50 +01:00
|
|
|
image->type = pCreateInfo->imageType;
|
|
|
|
image->info.width = pCreateInfo->extent.width;
|
|
|
|
image->info.height = pCreateInfo->extent.height;
|
|
|
|
image->info.depth = pCreateInfo->extent.depth;
|
|
|
|
image->info.samples = pCreateInfo->samples;
|
|
|
|
image->info.storage_samples = pCreateInfo->samples;
|
|
|
|
image->info.array_size = pCreateInfo->arrayLayers;
|
|
|
|
image->info.levels = pCreateInfo->mipLevels;
|
2019-09-24 15:33:39 +01:00
|
|
|
image->info.num_channels = vk_format_get_nr_components(format);
|
2019-09-23 15:14:50 +01:00
|
|
|
|
2019-09-24 15:33:39 +01:00
|
|
|
image->vk_format = format;
|
2019-09-23 15:14:50 +01:00
|
|
|
image->tiling = pCreateInfo->tiling;
|
|
|
|
image->usage = pCreateInfo->usage;
|
|
|
|
image->flags = pCreateInfo->flags;
|
|
|
|
image->plane_count = plane_count;
|
|
|
|
|
|
|
|
image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
|
|
|
|
if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
|
|
|
|
for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
|
|
|
|
if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
|
|
|
|
pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
|
|
|
|
image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
|
|
|
|
else
|
|
|
|
image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
|
|
|
|
}
|
|
|
|
|
2019-09-24 18:42:49 +01:00
|
|
|
const VkExternalMemoryImageCreateInfo *external_info =
|
|
|
|
vk_find_struct_const(pCreateInfo->pNext,
|
|
|
|
EXTERNAL_MEMORY_IMAGE_CREATE_INFO) ;
|
|
|
|
|
|
|
|
image->shareable = external_info;
|
2019-09-24 15:33:39 +01:00
|
|
|
if (!vk_format_is_depth_or_stencil(format) && !image->shareable) {
|
2019-09-23 15:14:50 +01:00
|
|
|
image->info.surf_index = &device->image_mrt_offset_counter;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (unsigned plane = 0; plane < image->plane_count; ++plane) {
|
2019-09-24 15:33:39 +01:00
|
|
|
radv_init_surface(device, image, &image->planes[plane].surface, plane, pCreateInfo, format);
|
2019-09-23 15:14:50 +01:00
|
|
|
}
|
|
|
|
|
2019-09-24 18:42:49 +01:00
|
|
|
bool delay_layout = external_info &&
|
|
|
|
(external_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID);
|
|
|
|
|
|
|
|
if (delay_layout) {
|
|
|
|
*pImage = radv_image_to_handle(image);
|
|
|
|
assert (!(image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT));
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2019-09-24 12:42:31 +01:00
|
|
|
ASSERTED VkResult result = radv_image_create_layout(device, *create_info, image);
|
2019-09-24 12:23:36 +01:00
|
|
|
assert(result == VK_SUCCESS);
|
2019-09-23 15:14:50 +01:00
|
|
|
|
|
|
|
if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
|
2017-02-04 14:56:20 +00:00
|
|
|
image->alignment = MAX2(image->alignment, 4096);
|
|
|
|
image->size = align64(image->size, image->alignment);
|
|
|
|
image->offset = 0;
|
|
|
|
|
|
|
|
image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
|
2019-01-27 23:28:05 +00:00
|
|
|
0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
|
2017-02-04 14:56:20 +00:00
|
|
|
if (!image->bo) {
|
2020-04-29 09:16:32 +01:00
|
|
|
vk_free2(&device->vk.alloc, alloc, image);
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
|
2017-02-04 14:56:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
*pImage = radv_image_to_handle(image);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2017-07-12 10:29:52 +01:00
|
|
|
static void
|
|
|
|
radv_image_view_make_descriptor(struct radv_image_view *iview,
|
|
|
|
struct radv_device *device,
|
2018-12-02 22:58:54 +00:00
|
|
|
VkFormat vk_format,
|
2017-08-21 04:56:33 +01:00
|
|
|
const VkComponentMapping *components,
|
2019-08-05 00:19:29 +01:00
|
|
|
bool is_storage_image, bool disable_compression,
|
|
|
|
unsigned plane_id, unsigned descriptor_plane_id)
|
2017-07-12 10:29:52 +01:00
|
|
|
{
|
2017-08-21 04:56:33 +01:00
|
|
|
struct radv_image *image = iview->image;
|
2018-07-16 19:51:26 +01:00
|
|
|
struct radv_image_plane *plane = &image->planes[plane_id];
|
|
|
|
const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
|
2017-07-12 10:29:52 +01:00
|
|
|
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
|
|
|
|
uint32_t blk_w;
|
2018-12-02 22:58:54 +00:00
|
|
|
union radv_descriptor *descriptor;
|
2017-08-21 21:08:10 +01:00
|
|
|
uint32_t hw_level = 0;
|
2017-07-12 10:29:52 +01:00
|
|
|
|
|
|
|
if (is_storage_image) {
|
2018-12-02 22:58:54 +00:00
|
|
|
descriptor = &iview->storage_descriptor;
|
2017-07-12 10:29:52 +01:00
|
|
|
} else {
|
2018-12-02 22:58:54 +00:00
|
|
|
descriptor = &iview->descriptor;
|
2017-07-12 10:29:52 +01:00
|
|
|
}
|
|
|
|
|
2018-12-02 22:58:54 +00:00
|
|
|
assert(vk_format_get_plane_count(vk_format) == 1);
|
|
|
|
assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
|
|
|
|
blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
|
2017-07-12 10:29:52 +01:00
|
|
|
|
2017-08-21 21:08:10 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9)
|
|
|
|
hw_level = iview->base_mip;
|
2019-06-25 08:23:04 +01:00
|
|
|
radv_make_texture_descriptor(device, image, is_storage_image,
|
|
|
|
iview->type,
|
|
|
|
vk_format,
|
|
|
|
components,
|
|
|
|
hw_level, hw_level + iview->level_count - 1,
|
|
|
|
iview->base_layer,
|
|
|
|
iview->base_layer + iview->layer_count - 1,
|
|
|
|
iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
|
|
|
|
iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
|
|
|
|
iview->extent.depth,
|
|
|
|
descriptor->plane_descriptors[descriptor_plane_id],
|
|
|
|
descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
|
2017-08-21 04:56:33 +01:00
|
|
|
|
|
|
|
const struct legacy_surf_level *base_level_info = NULL;
|
|
|
|
if (device->physical_device->rad_info.chip_class <= GFX9) {
|
|
|
|
if (is_stencil)
|
2018-07-16 19:51:26 +01:00
|
|
|
base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
|
2017-08-21 04:56:33 +01:00
|
|
|
else
|
2018-07-16 19:51:26 +01:00
|
|
|
base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
|
2017-08-21 04:56:33 +01:00
|
|
|
}
|
2017-07-12 10:29:52 +01:00
|
|
|
si_set_mutable_tex_desc_fields(device, image,
|
2017-08-21 04:56:33 +01:00
|
|
|
base_level_info,
|
2018-12-02 22:58:54 +00:00
|
|
|
plane_id,
|
2017-08-21 04:56:33 +01:00
|
|
|
iview->base_mip,
|
|
|
|
iview->base_mip,
|
2019-08-05 00:19:29 +01:00
|
|
|
blk_w, is_stencil, is_storage_image,
|
2019-08-16 00:13:00 +01:00
|
|
|
is_storage_image || disable_compression,
|
2019-08-05 00:19:29 +01:00
|
|
|
descriptor->plane_descriptors[descriptor_plane_id]);
|
2017-07-12 10:29:52 +01:00
|
|
|
}
|
|
|
|
|
2018-07-17 23:53:52 +01:00
|
|
|
static unsigned
|
|
|
|
radv_plane_from_aspect(VkImageAspectFlags mask)
|
|
|
|
{
|
|
|
|
switch(mask) {
|
|
|
|
case VK_IMAGE_ASPECT_PLANE_1_BIT:
|
|
|
|
return 1;
|
|
|
|
case VK_IMAGE_ASPECT_PLANE_2_BIT:
|
|
|
|
return 2;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
VkFormat
|
|
|
|
radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
|
|
|
|
{
|
|
|
|
switch(mask) {
|
|
|
|
case VK_IMAGE_ASPECT_PLANE_0_BIT:
|
|
|
|
return image->planes[0].format;
|
|
|
|
case VK_IMAGE_ASPECT_PLANE_1_BIT:
|
|
|
|
return image->planes[1].format;
|
|
|
|
case VK_IMAGE_ASPECT_PLANE_2_BIT:
|
|
|
|
return image->planes[2].format;
|
|
|
|
case VK_IMAGE_ASPECT_STENCIL_BIT:
|
|
|
|
return vk_format_stencil_only(image->vk_format);
|
|
|
|
case VK_IMAGE_ASPECT_DEPTH_BIT:
|
|
|
|
return vk_format_depth_only(image->vk_format);
|
2019-05-02 17:07:11 +01:00
|
|
|
case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
|
|
|
|
return vk_format_depth_only(image->vk_format);
|
2018-07-17 23:53:52 +01:00
|
|
|
default:
|
|
|
|
return image->vk_format;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void
|
|
|
|
radv_image_view_init(struct radv_image_view *iview,
|
|
|
|
struct radv_device *device,
|
2019-08-05 00:07:04 +01:00
|
|
|
const VkImageViewCreateInfo* pCreateInfo,
|
|
|
|
const struct radv_image_view_extra_create_info* extra_create_info)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
|
|
|
|
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
|
2017-07-12 10:29:52 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
switch (image->type) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
2017-05-02 00:49:14 +01:00
|
|
|
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
|
2016-10-07 00:16:09 +01:00
|
|
|
break;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
|
2017-05-02 00:49:14 +01:00
|
|
|
<= radv_minify(image->info.depth, range->baseMipLevel));
|
2016-10-07 00:16:09 +01:00
|
|
|
break;
|
2016-10-11 01:43:09 +01:00
|
|
|
default:
|
|
|
|
unreachable("bad VkImageType");
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
iview->image = image;
|
|
|
|
iview->bo = image->bo;
|
|
|
|
iview->type = pCreateInfo->viewType;
|
2018-07-17 23:53:52 +01:00
|
|
|
iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
|
2018-12-02 22:58:54 +00:00
|
|
|
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
|
|
|
|
iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
|
2019-09-24 15:33:39 +01:00
|
|
|
|
2018-12-02 22:58:54 +00:00
|
|
|
iview->vk_format = pCreateInfo->format;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2019-09-24 15:33:39 +01:00
|
|
|
/* If the image has an Android external format, pCreateInfo->format will be
|
|
|
|
* VK_FORMAT_UNDEFINED. */
|
|
|
|
if (iview->vk_format == VK_FORMAT_UNDEFINED)
|
|
|
|
iview->vk_format = image->vk_format;
|
|
|
|
|
2016-11-15 06:46:50 +00:00
|
|
|
if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
|
|
|
|
iview->vk_format = vk_format_stencil_only(iview->vk_format);
|
|
|
|
} else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
|
|
|
|
iview->vk_format = vk_format_depth_only(iview->vk_format);
|
|
|
|
}
|
|
|
|
|
2017-08-21 05:04:02 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
|
|
|
iview->extent = (VkExtent3D) {
|
|
|
|
.width = image->info.width,
|
|
|
|
.height = image->info.height,
|
|
|
|
.depth = image->info.depth,
|
|
|
|
};
|
|
|
|
} else {
|
|
|
|
iview->extent = (VkExtent3D) {
|
|
|
|
.width = radv_minify(image->info.width , range->baseMipLevel),
|
|
|
|
.height = radv_minify(image->info.height, range->baseMipLevel),
|
|
|
|
.depth = radv_minify(image->info.depth , range->baseMipLevel),
|
|
|
|
};
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2018-07-17 23:53:52 +01:00
|
|
|
if (iview->vk_format != image->planes[iview->plane_id].format) {
|
2018-01-29 04:15:09 +00:00
|
|
|
unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
|
|
|
|
unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
|
|
|
|
unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
|
|
|
|
unsigned img_bh = vk_format_get_blockheight(image->vk_format);
|
|
|
|
|
|
|
|
iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
|
|
|
|
iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
|
|
|
|
|
|
|
|
/* Comment ported from amdvlk -
|
|
|
|
* If we have the following image:
|
|
|
|
* Uncompressed pixels Compressed block sizes (4x4)
|
|
|
|
* mip0: 22 x 22 6 x 6
|
|
|
|
* mip1: 11 x 11 3 x 3
|
|
|
|
* mip2: 5 x 5 2 x 2
|
|
|
|
* mip3: 2 x 2 1 x 1
|
|
|
|
* mip4: 1 x 1 1 x 1
|
|
|
|
*
|
|
|
|
* On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
|
|
|
|
* calculating the degradation of the block sizes down the mip-chain as follows (straight-up
|
|
|
|
* divide-by-two integer math):
|
|
|
|
* mip0: 6x6
|
|
|
|
* mip1: 3x3
|
|
|
|
* mip2: 1x1
|
|
|
|
* mip3: 1x1
|
|
|
|
*
|
|
|
|
* This means that mip2 will be missing texels.
|
|
|
|
*
|
|
|
|
* Fix this by calculating the base mip's width and height, then convert that, and round it
|
|
|
|
* back up to get the level 0 size.
|
|
|
|
* Clamp the converted size between the original values, and next power of two, which
|
|
|
|
* means we don't oversize the image.
|
|
|
|
*/
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
|
|
|
vk_format_is_compressed(image->vk_format) &&
|
|
|
|
!vk_format_is_compressed(iview->vk_format)) {
|
|
|
|
unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
|
|
|
|
unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
|
|
|
|
|
|
|
|
lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
|
|
|
|
lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
|
|
|
|
|
|
|
|
lvl_width <<= range->baseMipLevel;
|
|
|
|
lvl_height <<= range->baseMipLevel;
|
|
|
|
|
2018-07-16 19:51:26 +01:00
|
|
|
iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
|
|
|
|
iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
|
2018-01-29 04:15:09 +00:00
|
|
|
}
|
2017-08-21 04:58:27 +01:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
iview->base_layer = range->baseArrayLayer;
|
|
|
|
iview->layer_count = radv_get_layerCount(image, range);
|
|
|
|
iview->base_mip = range->baseMipLevel;
|
2017-08-21 04:56:33 +01:00
|
|
|
iview->level_count = radv_get_levelCount(image, range);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2019-08-05 00:19:29 +01:00
|
|
|
bool disable_compression = extra_create_info ? extra_create_info->disable_compression: false;
|
2018-12-02 22:58:54 +00:00
|
|
|
for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
|
|
|
|
VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
|
2019-08-05 00:19:29 +01:00
|
|
|
radv_image_view_make_descriptor(iview, device, format,
|
|
|
|
&pCreateInfo->components,
|
|
|
|
false, disable_compression,
|
|
|
|
iview->plane_id + i, i);
|
|
|
|
radv_image_view_make_descriptor(iview, device,
|
|
|
|
format, &pCreateInfo->components,
|
|
|
|
true, disable_compression,
|
|
|
|
iview->plane_id + i, i);
|
2018-12-02 22:58:54 +00:00
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool radv_layout_is_htile_compressed(const struct radv_image *image,
|
2017-05-15 22:00:17 +01:00
|
|
|
VkImageLayout layout,
|
2019-08-04 22:48:43 +01:00
|
|
|
bool in_render_loop,
|
2017-05-15 22:00:17 +01:00
|
|
|
unsigned queue_mask)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2020-04-09 10:37:27 +01:00
|
|
|
if (radv_image_is_tc_compat_htile(image)) {
|
|
|
|
if (layout == VK_IMAGE_LAYOUT_GENERAL &&
|
|
|
|
!in_render_loop &&
|
|
|
|
!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
|
|
|
|
/* It should be safe to enable TC-compat HTILE with
|
|
|
|
* VK_IMAGE_LAYOUT_GENERAL if we are not in a render
|
|
|
|
* loop and if the image doesn't have the storage bit
|
|
|
|
* set. This improves performance for apps that use
|
|
|
|
* GENERAL for the main depth pass because this allows
|
|
|
|
* compression and this reduces the number of
|
|
|
|
* decompressions from/to GENERAL.
|
|
|
|
*/
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-08-16 00:06:55 +01:00
|
|
|
return layout != VK_IMAGE_LAYOUT_GENERAL;
|
2020-04-09 10:37:27 +01:00
|
|
|
}
|
2017-05-09 07:26:07 +01:00
|
|
|
|
2018-04-06 14:37:28 +01:00
|
|
|
return radv_image_has_htile(image) &&
|
2017-05-15 00:23:24 +01:00
|
|
|
(layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
|
2019-12-09 12:56:24 +00:00
|
|
|
layout == VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR ||
|
|
|
|
layout == VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR ||
|
2019-03-17 02:18:29 +00:00
|
|
|
(layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
|
|
|
|
queue_mask == (1u << RADV_QUEUE_GENERAL)));
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2016-12-26 23:57:36 +00:00
|
|
|
bool radv_layout_can_fast_clear(const struct radv_image *image,
|
|
|
|
VkImageLayout layout,
|
2019-08-04 22:48:43 +01:00
|
|
|
bool in_render_loop,
|
2016-12-26 23:57:36 +00:00
|
|
|
unsigned queue_mask)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2019-03-17 02:18:29 +00:00
|
|
|
return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
|
2016-12-17 20:25:32 +00:00
|
|
|
}
|
|
|
|
|
2019-08-05 00:38:42 +01:00
|
|
|
bool radv_layout_dcc_compressed(const struct radv_device *device,
|
|
|
|
const struct radv_image *image,
|
2017-12-28 01:54:10 +00:00
|
|
|
VkImageLayout layout,
|
2019-08-04 22:48:43 +01:00
|
|
|
bool in_render_loop,
|
2017-12-28 01:54:10 +00:00
|
|
|
unsigned queue_mask)
|
|
|
|
{
|
|
|
|
/* Don't compress compute transfer dst, as image stores are not supported. */
|
|
|
|
if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
|
2019-08-16 00:13:00 +01:00
|
|
|
(queue_mask & (1u << RADV_QUEUE_COMPUTE)))
|
2017-12-28 01:54:10 +00:00
|
|
|
return false;
|
|
|
|
|
2019-08-16 00:06:55 +01:00
|
|
|
return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
|
2017-12-28 01:54:10 +00:00
|
|
|
}
|
|
|
|
|
2016-12-17 20:25:32 +00:00
|
|
|
|
2017-01-31 05:18:33 +00:00
|
|
|
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
|
|
|
|
{
|
|
|
|
if (!image->exclusive)
|
|
|
|
return image->queue_family_mask;
|
2019-07-03 01:25:19 +01:00
|
|
|
if (family == VK_QUEUE_FAMILY_EXTERNAL ||
|
|
|
|
family == VK_QUEUE_FAMILY_FOREIGN_EXT)
|
2017-07-15 01:08:01 +01:00
|
|
|
return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
|
2017-01-31 05:18:33 +00:00
|
|
|
if (family == VK_QUEUE_FAMILY_IGNORED)
|
|
|
|
return 1u << queue_family;
|
|
|
|
return 1u << family;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateImage(VkDevice device,
|
|
|
|
const VkImageCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkImage *pImage)
|
|
|
|
{
|
2018-01-04 17:38:32 +00:00
|
|
|
#ifdef ANDROID
|
|
|
|
const VkNativeBufferANDROID *gralloc_info =
|
|
|
|
vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
|
|
|
|
|
|
|
|
if (gralloc_info)
|
|
|
|
return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
|
|
|
|
pAllocator, pImage);
|
|
|
|
#endif
|
|
|
|
|
2017-11-16 16:27:01 +00:00
|
|
|
const struct wsi_image_create_info *wsi_info =
|
|
|
|
vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
|
|
|
|
bool scanout = wsi_info && wsi_info->scanout;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
return radv_image_create(device,
|
|
|
|
&(struct radv_image_create_info) {
|
|
|
|
.vk_info = pCreateInfo,
|
2017-11-16 16:27:01 +00:00
|
|
|
.scanout = scanout,
|
|
|
|
},
|
2016-10-07 00:16:09 +01:00
|
|
|
pAllocator,
|
|
|
|
pImage);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyImage(VkDevice _device, VkImage _image,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
2017-02-04 14:56:20 +00:00
|
|
|
RADV_FROM_HANDLE(radv_image, image, _image);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
if (!image)
|
2016-10-07 00:16:09 +01:00
|
|
|
return;
|
|
|
|
|
2017-02-04 14:56:20 +00:00
|
|
|
if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
|
|
|
|
device->ws->buffer_destroy(image->bo);
|
|
|
|
|
2018-01-04 17:38:32 +00:00
|
|
|
if (image->owned_memory != VK_NULL_HANDLE)
|
|
|
|
radv_FreeMemory(_device, image->owned_memory, pAllocator);
|
|
|
|
|
2020-04-29 13:57:20 +01:00
|
|
|
vk_object_base_finish(&image->base);
|
2020-04-29 09:16:32 +01:00
|
|
|
vk_free2(&device->vk.alloc, pAllocator, image);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void radv_GetImageSubresourceLayout(
|
2017-08-15 06:35:52 +01:00
|
|
|
VkDevice _device,
|
2016-10-07 00:16:09 +01:00
|
|
|
VkImage _image,
|
|
|
|
const VkImageSubresource* pSubresource,
|
|
|
|
VkSubresourceLayout* pLayout)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_image, image, _image);
|
2017-08-15 06:35:52 +01:00
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
2016-10-07 00:16:09 +01:00
|
|
|
int level = pSubresource->mipLevel;
|
|
|
|
int layer = pSubresource->arrayLayer;
|
2018-07-17 23:53:52 +01:00
|
|
|
|
|
|
|
unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
|
|
|
|
|
|
|
|
struct radv_image_plane *plane = &image->planes[plane_id];
|
2018-07-16 19:51:26 +01:00
|
|
|
struct radeon_surf *surface = &plane->surface;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-08-15 06:35:52 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
2020-01-03 10:25:31 +00:00
|
|
|
uint64_t level_offset = surface->is_linear ? surface->u.gfx9.offset[level] : 0;
|
|
|
|
|
|
|
|
pLayout->offset = plane->offset + level_offset + surface->u.gfx9.surf_slice_size * layer;
|
2019-05-06 15:17:26 +01:00
|
|
|
if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
|
|
|
|
image->vk_format == VK_FORMAT_R32G32B32_SINT ||
|
|
|
|
image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
|
|
|
|
/* Adjust the number of bytes between each row because
|
|
|
|
* the pitch is actually the number of components per
|
|
|
|
* row.
|
|
|
|
*/
|
|
|
|
pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
|
|
|
|
} else {
|
2020-01-03 10:25:31 +00:00
|
|
|
uint32_t pitch = surface->is_linear ? surface->u.gfx9.pitch[level] : surface->u.gfx9.surf_pitch;
|
|
|
|
|
2019-05-06 15:17:26 +01:00
|
|
|
assert(util_is_power_of_two_nonzero(surface->bpe));
|
2020-01-03 10:25:31 +00:00
|
|
|
pLayout->rowPitch = pitch * surface->bpe;
|
2019-05-06 15:17:26 +01:00
|
|
|
}
|
|
|
|
|
2017-08-15 06:35:52 +01:00
|
|
|
pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
|
|
|
|
pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
|
|
|
|
pLayout->size = surface->u.gfx9.surf_slice_size;
|
|
|
|
if (image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pLayout->size *= u_minify(image->info.depth, level);
|
|
|
|
} else {
|
2018-07-16 19:51:26 +01:00
|
|
|
pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
|
2017-08-15 06:35:52 +01:00
|
|
|
pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
|
2017-11-14 18:31:39 +00:00
|
|
|
pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
|
|
|
pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
|
|
|
pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
|
2017-08-15 06:35:52 +01:00
|
|
|
if (image->type == VK_IMAGE_TYPE_3D)
|
|
|
|
pLayout->size *= u_minify(image->info.depth, level);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateImageView(VkDevice _device,
|
|
|
|
const VkImageViewCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkImageView *pView)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
struct radv_image_view *view;
|
|
|
|
|
2020-04-29 09:16:32 +01:00
|
|
|
view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
|
2016-10-07 00:16:09 +01:00
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (view == NULL)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-04-29 13:57:20 +01:00
|
|
|
vk_object_base_init(&device->vk, &view->base,
|
|
|
|
VK_OBJECT_TYPE_IMAGE_VIEW);
|
|
|
|
|
2019-08-05 00:07:04 +01:00
|
|
|
radv_image_view_init(view, device, pCreateInfo, NULL);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
*pView = radv_image_view_to_handle(view);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyImageView(VkDevice _device, VkImageView _iview,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_image_view, iview, _iview);
|
|
|
|
|
|
|
|
if (!iview)
|
|
|
|
return;
|
2020-04-29 13:57:20 +01:00
|
|
|
|
|
|
|
vk_object_base_finish(&iview->base);
|
2020-04-29 09:16:32 +01:00
|
|
|
vk_free2(&device->vk.alloc, pAllocator, iview);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void radv_buffer_view_init(struct radv_buffer_view *view,
|
|
|
|
struct radv_device *device,
|
2017-09-12 18:08:45 +01:00
|
|
|
const VkBufferViewCreateInfo* pCreateInfo)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
|
|
|
|
|
|
|
|
view->bo = buffer->bo;
|
|
|
|
view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
|
|
|
|
buffer->size - pCreateInfo->offset : pCreateInfo->range;
|
|
|
|
view->vk_format = pCreateInfo->format;
|
|
|
|
|
|
|
|
radv_make_buffer_descriptor(device, buffer, view->vk_format,
|
|
|
|
pCreateInfo->offset, view->range, view->state);
|
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_CreateBufferView(VkDevice _device,
|
|
|
|
const VkBufferViewCreateInfo *pCreateInfo,
|
|
|
|
const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkBufferView *pView)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
struct radv_buffer_view *view;
|
|
|
|
|
2020-04-29 09:16:32 +01:00
|
|
|
view = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*view), 8,
|
2016-10-07 00:16:09 +01:00
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (!view)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2020-04-29 13:57:20 +01:00
|
|
|
vk_object_base_init(&device->vk, &view->base,
|
|
|
|
VK_OBJECT_TYPE_BUFFER_VIEW);
|
|
|
|
|
2017-09-12 18:08:45 +01:00
|
|
|
radv_buffer_view_init(view, device, pCreateInfo);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
*pView = radv_buffer_view_to_handle(view);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
|
|
|
|
const VkAllocationCallbacks *pAllocator)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
|
|
|
|
|
|
|
|
if (!view)
|
|
|
|
return;
|
|
|
|
|
2020-04-29 13:57:20 +01:00
|
|
|
vk_object_base_finish(&view->base);
|
2020-04-29 09:16:32 +01:00
|
|
|
vk_free2(&device->vk.alloc, pAllocator, view);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|