radv: Pass no_metadata_planes info in to ac_surface.
Also do not allocate aux surfaces for multi-plane images. I may have messed up and used plane 1 offsets for the other planes as well. I cannot imagine that sharing aux surfaces between the planes will work well. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>
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@ -1374,6 +1374,12 @@ radv_image_create_layout(struct radv_device *device,
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info.height /= desc->height_divisor;
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}
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if (create_info.no_metadata_planes || image->plane_count > 1) {
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image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC |
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RADEON_SURF_NO_FMASK |
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RADEON_SURF_NO_HTILE;
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}
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device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
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image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
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@ -1383,44 +1389,39 @@ radv_image_create_layout(struct radv_device *device,
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image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
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}
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if (!create_info.no_metadata_planes) {
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/* Try to enable DCC first. */
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if (radv_image_can_enable_dcc(device, image)) {
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radv_image_alloc_dcc(image);
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if (image->info.samples > 1) {
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/* CMASK should be enabled because DCC fast
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* clear with MSAA needs it.
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*/
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assert(radv_image_can_enable_cmask(image));
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radv_image_alloc_cmask(device, image);
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}
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} else {
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/* When DCC cannot be enabled, try CMASK. */
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radv_image_disable_dcc(image);
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if (radv_image_can_enable_cmask(image)) {
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radv_image_alloc_cmask(device, image);
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}
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}
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/* Try to enable FMASK for multisampled images. */
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if (image->planes[0].surface.fmask_size) {
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radv_image_alloc_fmask(device, image);
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if (radv_use_tc_compat_cmask_for_image(device, image))
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image->tc_compatible_cmask = true;
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} else {
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/* Otherwise, try to enable HTILE for depth surfaces. */
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if (radv_image_can_enable_htile(image) &&
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!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
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image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
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radv_image_alloc_htile(device, image);
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} else {
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radv_image_disable_htile(image);
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}
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/* Try to enable DCC first. */
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if (radv_image_can_enable_dcc(device, image)) {
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radv_image_alloc_dcc(image);
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if (image->info.samples > 1) {
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/* CMASK should be enabled because DCC fast
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* clear with MSAA needs it.
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*/
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assert(radv_image_can_enable_cmask(image));
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radv_image_alloc_cmask(device, image);
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}
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} else {
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/* When DCC cannot be enabled, try CMASK. */
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radv_image_disable_dcc(image);
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radv_image_disable_htile(image);
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if (radv_image_can_enable_cmask(image)) {
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radv_image_alloc_cmask(device, image);
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}
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}
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/* Try to enable FMASK for multisampled images. */
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if (image->planes[0].surface.fmask_size) {
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radv_image_alloc_fmask(device, image);
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if (radv_use_tc_compat_cmask_for_image(device, image))
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image->tc_compatible_cmask = true;
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} else {
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/* Otherwise, try to enable HTILE for depth surfaces. */
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if (radv_image_can_enable_htile(image) &&
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!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
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image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
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radv_image_alloc_htile(device, image);
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} else {
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radv_image_disable_htile(image);
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}
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}
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assert(image->planes[0].surface.surf_size);
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