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amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile 

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
This commit is contained in:
Marek Olšák 2020-05-02 09:19:18 -04:00 committed by Marge Bot
parent cf61f635ff
commit 56e37374dd
7 changed files with 28 additions and 26 deletions
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11
src/amd/common/ac_surface.c
View File

@ -1178,8 +1178,11 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
assert(in->flags.metaPipeUnaligned == 0);
assert(in->flags.metaRbUnaligned == 0);
hin.hTileFlags.pipeAligned = 1;
hin.hTileFlags.rbAligned = 1;
hin.depthFlags = in->flags;
hin.swizzleMode = in->swizzleMode;
hin.unalignedWidth = in->width;
@ -1192,8 +1195,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.htile.rb_aligned = hin.hTileFlags.rbAligned;
surf->u.gfx9.htile.pipe_aligned = hin.hTileFlags.pipeAligned;
surf->htile_size = hout.htileBytes;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
@ -1604,7 +1605,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
else
AddrSurfInfoIn.numSlices = config->info.array_size;
/* This is propagated to HTILE/DCC. */
/* This is propagated to DCC. It must be 0 for HTILE and CMASK. */
AddrSurfInfoIn.flags.metaPipeUnaligned = 0;
AddrSurfInfoIn.flags.metaRbUnaligned = 0;

1
src/amd/common/ac_surface.h
View File

@ -150,7 +150,6 @@ struct gfx9_surf_layout {
struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */
struct gfx9_surf_meta_flags dcc; /* metadata of color */
struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */
enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */
uint16_t surf_pitch; /* in blocks */

4
src/amd/vulkan/radv_device.c
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@ -6810,10 +6810,10 @@ radv_initialise_ds_surface(struct radv_device *device,
iview->image->htile_offset;
ds->db_htile_data_base = va >> 8;
ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
S_028ABC_PIPE_ALIGNED(1);
if (device->physical_device->rad_info.chip_class == GFX9) {
ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
}
}
} else {

14
src/amd/vulkan/radv_image.c
View File

@ -609,12 +609,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
C_00A018_META_PIPE_ALIGNED;
if (meta_va) {
struct gfx9_surf_meta_flags meta;
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
else
meta = plane->surface.u.gfx9.htile;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
@ -637,12 +638,13 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
C_008F24_META_PIPE_ALIGNED &
C_008F24_META_RB_ALIGNED;
if (meta_va) {
struct gfx9_surf_meta_flags meta;
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (image->dcc_offset)
meta = plane->surface.u.gfx9.dcc;
else
meta = plane->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |

14
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@ -349,12 +349,13 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
state[6] &= C_00A018_META_DATA_ADDRESS_LO & C_00A018_META_PIPE_ALIGNED;
if (meta_va) {
struct gfx9_surf_meta_flags meta;
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (tex->surface.dcc_offset)
meta = tex->surface.u.gfx9.dcc;
else
meta = tex->surface.u.gfx9.htile;
state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
@ -376,12 +377,13 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
state[5] &=
C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
if (meta_va) {
struct gfx9_surf_meta_flags meta;
struct gfx9_surf_meta_flags meta = {
.rb_aligned = 1,
.pipe_aligned = 1,
};
if (tex->surface.dcc_offset)
meta = tex->surface.u.gfx9.dcc;
else
meta = tex->surface.u.gfx9.htile;
state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |

4
src/gallium/drivers/radeonsi/si_state.c
View File

@ -2540,9 +2540,9 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su
surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
surf->db_htile_surface =
S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
if (sctx->chip_class == GFX9) {
surf->db_htile_surface |= S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
}
}
} else {

6
src/gallium/drivers/radeonsi/si_texture.c
View File

@ -1072,11 +1072,9 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
if (tex->surface.htile_offset) {
u_log_printf(log,
" HTile: offset=%" PRIu64 ", size=%u, alignment=%u, "
"rb_aligned=%u, pipe_aligned=%u\n",
" HTile: offset=%" PRIu64 ", size=%u, alignment=%u\n",
tex->surface.htile_offset, tex->surface.htile_size,
tex->surface.htile_alignment, tex->surface.u.gfx9.htile.rb_aligned,
tex->surface.u.gfx9.htile.pipe_aligned);
tex->surface.htile_alignment);
}
if (tex->surface.dcc_offset) {