2017-11-24 07:15:14 +00:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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2018-08-19 08:31:46 +01:00
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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2017-11-24 07:15:14 +00:00
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*
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2018-08-19 08:31:46 +01:00
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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2017-11-24 07:15:14 +00:00
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*
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2018-08-19 08:31:46 +01:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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2017-11-24 07:15:14 +00:00
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*/
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2018-07-31 07:49:34 +01:00
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/**
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* @file iris_resource.c
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*
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* Resources are images, buffers, and other objects used by the GPU.
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*
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* XXX: explain resources
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*/
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2017-11-24 07:15:14 +00:00
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#include <stdio.h>
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#include <errno.h>
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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#include "pipe/p_context.h"
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#include "pipe/p_screen.h"
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2018-05-29 01:14:43 +01:00
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#include "util/os_memory.h"
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#include "util/u_cpu_detect.h"
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2017-11-24 07:15:14 +00:00
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#include "util/u_inlines.h"
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#include "util/u_format.h"
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2018-06-07 09:25:35 +01:00
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#include "util/u_transfer.h"
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2018-08-08 22:54:09 +01:00
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#include "util/u_transfer_helper.h"
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2017-11-24 07:15:14 +00:00
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#include "util/u_upload_mgr.h"
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#include "util/ralloc.h"
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2018-01-20 02:57:30 +00:00
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#include "iris_batch.h"
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#include "iris_context.h"
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2017-11-24 07:15:14 +00:00
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#include "iris_resource.h"
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#include "iris_screen.h"
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2019-04-05 23:39:51 +01:00
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#include "intel/dev/gen_debug.h"
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2018-05-29 01:14:43 +01:00
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#include "isl/isl.h"
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2017-11-24 07:15:14 +00:00
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#include "drm-uapi/drm_fourcc.h"
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#include "drm-uapi/i915_drm.h"
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enum modifier_priority {
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MODIFIER_PRIORITY_INVALID = 0,
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MODIFIER_PRIORITY_LINEAR,
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MODIFIER_PRIORITY_X,
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MODIFIER_PRIORITY_Y,
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MODIFIER_PRIORITY_Y_CCS,
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};
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static const uint64_t priority_to_modifier[] = {
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[MODIFIER_PRIORITY_INVALID] = DRM_FORMAT_MOD_INVALID,
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[MODIFIER_PRIORITY_LINEAR] = DRM_FORMAT_MOD_LINEAR,
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[MODIFIER_PRIORITY_X] = I915_FORMAT_MOD_X_TILED,
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[MODIFIER_PRIORITY_Y] = I915_FORMAT_MOD_Y_TILED,
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[MODIFIER_PRIORITY_Y_CCS] = I915_FORMAT_MOD_Y_TILED_CCS,
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};
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static bool
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modifier_is_supported(const struct gen_device_info *devinfo,
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uint64_t modifier)
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{
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/* XXX: do something real */
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switch (modifier) {
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_X_TILED:
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case DRM_FORMAT_MOD_LINEAR:
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return true;
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case I915_FORMAT_MOD_Y_TILED_CCS:
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case DRM_FORMAT_MOD_INVALID:
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default:
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return false;
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}
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}
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static uint64_t
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select_best_modifier(struct gen_device_info *devinfo,
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const uint64_t *modifiers,
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int count)
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{
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enum modifier_priority prio = MODIFIER_PRIORITY_INVALID;
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for (int i = 0; i < count; i++) {
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if (!modifier_is_supported(devinfo, modifiers[i]))
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continue;
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switch (modifiers[i]) {
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case I915_FORMAT_MOD_Y_TILED_CCS:
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prio = MAX2(prio, MODIFIER_PRIORITY_Y_CCS);
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break;
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case I915_FORMAT_MOD_Y_TILED:
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prio = MAX2(prio, MODIFIER_PRIORITY_Y);
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break;
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case I915_FORMAT_MOD_X_TILED:
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prio = MAX2(prio, MODIFIER_PRIORITY_X);
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break;
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case DRM_FORMAT_MOD_LINEAR:
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prio = MAX2(prio, MODIFIER_PRIORITY_LINEAR);
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break;
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case DRM_FORMAT_MOD_INVALID:
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default:
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break;
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}
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}
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return priority_to_modifier[prio];
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}
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static enum isl_surf_dim
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target_to_isl_surf_dim(enum pipe_texture_target target)
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{
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switch (target) {
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case PIPE_BUFFER:
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case PIPE_TEXTURE_1D:
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case PIPE_TEXTURE_1D_ARRAY:
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return ISL_SURF_DIM_1D;
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_RECT:
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_CUBE_ARRAY:
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return ISL_SURF_DIM_2D;
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case PIPE_TEXTURE_3D:
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return ISL_SURF_DIM_3D;
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case PIPE_MAX_TEXTURE_TYPES:
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break;
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}
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unreachable("invalid texture type");
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}
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2019-03-26 07:25:31 +00:00
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static void
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iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
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enum pipe_format pfmt,
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int max,
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uint64_t *modifiers,
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unsigned int *external_only,
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int *count)
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{
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struct iris_screen *screen = (void *) pscreen;
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const struct gen_device_info *devinfo = &screen->devinfo;
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uint64_t all_modifiers[] = {
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DRM_FORMAT_MOD_LINEAR,
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I915_FORMAT_MOD_X_TILED,
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I915_FORMAT_MOD_Y_TILED,
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// XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS,
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};
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int supported_mods = 0;
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for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
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if (!modifier_is_supported(devinfo, all_modifiers[i]))
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continue;
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if (supported_mods < max) {
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if (modifiers)
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modifiers[supported_mods] = all_modifiers[i];
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if (external_only)
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external_only[supported_mods] = util_format_is_yuv(pfmt);
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}
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supported_mods++;
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}
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*count = supported_mods;
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}
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2017-11-24 07:15:14 +00:00
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static isl_surf_usage_flags_t
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pipe_bind_to_isl_usage(unsigned bindings)
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{
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isl_surf_usage_flags_t usage = 0;
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if (bindings & PIPE_BIND_RENDER_TARGET)
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usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
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2018-04-25 23:25:33 +01:00
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if (bindings & PIPE_BIND_SAMPLER_VIEW)
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usage |= ISL_SURF_USAGE_TEXTURE_BIT;
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if (bindings & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SHADER_BUFFER))
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2017-11-24 07:15:14 +00:00
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usage |= ISL_SURF_USAGE_STORAGE_BIT;
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if (bindings & PIPE_BIND_DISPLAY_TARGET)
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usage |= ISL_SURF_USAGE_DISPLAY_BIT;
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return usage;
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}
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2018-07-30 23:08:02 +01:00
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struct pipe_resource *
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iris_resource_get_separate_stencil(struct pipe_resource *p_res)
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{
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/* For packed depth-stencil, we treat depth as the primary resource
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* and store S8 as the "second plane" resource.
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*/
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return p_res->next;
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}
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2018-08-08 22:54:09 +01:00
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static void
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iris_resource_set_separate_stencil(struct pipe_resource *p_res,
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struct pipe_resource *stencil)
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{
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assert(util_format_has_depth(util_format_description(p_res->format)));
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2018-08-09 17:19:58 +01:00
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pipe_resource_reference(&p_res->next, stencil);
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2018-08-08 22:54:09 +01:00
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}
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2018-08-04 00:18:09 +01:00
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void
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iris_get_depth_stencil_resources(struct pipe_resource *res,
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struct iris_resource **out_z,
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struct iris_resource **out_s)
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{
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if (!res) {
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*out_z = NULL;
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*out_s = NULL;
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return;
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}
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2019-02-14 06:12:01 +00:00
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if (res->format != PIPE_FORMAT_S8_UINT) {
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2018-08-04 00:18:09 +01:00
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*out_z = (void *) res;
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*out_s = (void *) iris_resource_get_separate_stencil(res);
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} else {
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*out_z = NULL;
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*out_s = (void *) res;
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}
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}
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2018-12-07 19:54:16 +00:00
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void
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2018-12-07 18:46:04 +00:00
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iris_resource_disable_aux(struct iris_resource *res)
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{
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iris_bo_unreference(res->aux.bo);
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2019-02-15 22:45:05 +00:00
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iris_bo_unreference(res->aux.clear_color_bo);
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2018-12-07 18:46:04 +00:00
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free(res->aux.state);
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res->aux.usage = ISL_AUX_USAGE_NONE;
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2018-12-10 07:12:33 +00:00
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res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
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2019-03-27 21:42:12 +00:00
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res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
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2018-12-07 18:46:04 +00:00
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res->aux.surf.size_B = 0;
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res->aux.bo = NULL;
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2019-02-15 22:45:05 +00:00
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res->aux.clear_color_bo = NULL;
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2018-12-07 18:46:04 +00:00
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res->aux.state = NULL;
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}
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2017-11-24 07:15:14 +00:00
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static void
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iris_resource_destroy(struct pipe_screen *screen,
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struct pipe_resource *resource)
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{
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struct iris_resource *res = (struct iris_resource *)resource;
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2018-12-07 18:46:04 +00:00
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iris_resource_disable_aux(res);
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2017-11-24 07:15:14 +00:00
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iris_bo_unreference(res->bo);
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2018-06-16 17:56:59 +01:00
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free(res);
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2017-11-24 07:15:14 +00:00
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}
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static struct iris_resource *
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iris_alloc_resource(struct pipe_screen *pscreen,
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const struct pipe_resource *templ)
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{
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struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
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if (!res)
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return NULL;
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res->base = *templ;
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res->base.screen = pscreen;
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pipe_reference_init(&res->base.reference, 1);
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2018-12-07 19:02:50 +00:00
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res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
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2019-03-27 21:42:12 +00:00
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res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE;
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2018-12-07 19:02:50 +00:00
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2017-11-24 07:15:14 +00:00
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return res;
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}
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2018-12-07 19:54:02 +00:00
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unsigned
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iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
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{
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if (res->surf.dim == ISL_SURF_DIM_3D)
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return minify(res->surf.logical_level0_px.depth, level);
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else
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return res->surf.logical_level0_px.array_len;
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}
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static enum isl_aux_state **
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create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
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{
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uint32_t total_slices = 0;
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for (uint32_t level = 0; level < res->surf.levels; level++)
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total_slices += iris_get_num_logical_layers(res, level);
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const size_t per_level_array_size =
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res->surf.levels * sizeof(enum isl_aux_state *);
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/* We're going to allocate a single chunk of data for both the per-level
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* reference array and the arrays of aux_state. This makes cleanup
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* significantly easier.
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*/
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const size_t total_size =
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per_level_array_size + total_slices * sizeof(enum isl_aux_state);
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void *data = malloc(total_size);
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if (!data)
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return NULL;
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enum isl_aux_state **per_level_arr = data;
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enum isl_aux_state *s = data + per_level_array_size;
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for (uint32_t level = 0; level < res->surf.levels; level++) {
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per_level_arr[level] = s;
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const unsigned level_layers = iris_get_num_logical_layers(res, level);
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for (uint32_t a = 0; a < level_layers; a++)
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*(s++) = initial;
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}
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assert((void *)s == data + total_size);
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return per_level_arr;
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}
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/**
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* Allocate the initial aux surface for a resource based on aux.usage
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*/
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static bool
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iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res)
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{
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|
|
struct isl_device *isl_dev = &screen->isl_dev;
|
|
|
|
enum isl_aux_state initial_state;
|
|
|
|
UNUSED bool ok = false;
|
|
|
|
uint8_t memset_value = 0;
|
|
|
|
uint32_t alloc_flags = 0;
|
2019-02-15 22:45:05 +00:00
|
|
|
const struct gen_device_info *devinfo = &screen->devinfo;
|
|
|
|
const unsigned clear_color_state_size = devinfo->gen >= 10 ?
|
|
|
|
screen->isl_dev.ss.clear_color_state_size :
|
2019-03-26 23:28:10 +00:00
|
|
|
(devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0);
|
2018-12-07 19:54:02 +00:00
|
|
|
|
|
|
|
assert(!res->aux.bo);
|
|
|
|
|
|
|
|
switch (res->aux.usage) {
|
|
|
|
case ISL_AUX_USAGE_NONE:
|
|
|
|
res->aux.surf.size_B = 0;
|
|
|
|
break;
|
|
|
|
case ISL_AUX_USAGE_HIZ:
|
|
|
|
initial_state = ISL_AUX_STATE_AUX_INVALID;
|
|
|
|
memset_value = 0;
|
|
|
|
ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf);
|
|
|
|
break;
|
|
|
|
case ISL_AUX_USAGE_MCS:
|
|
|
|
/* The Ivybridge PRM, Vol 2 Part 1 p326 says:
|
|
|
|
*
|
|
|
|
* "When MCS buffer is enabled and bound to MSRT, it is required
|
|
|
|
* that it is cleared prior to any rendering."
|
|
|
|
*
|
|
|
|
* Since we only use the MCS buffer for rendering, we just clear it
|
|
|
|
* immediately on allocation. The clear value for MCS buffers is all
|
|
|
|
* 1's, so we simply memset it to 0xff.
|
|
|
|
*/
|
|
|
|
initial_state = ISL_AUX_STATE_CLEAR;
|
|
|
|
memset_value = 0xFF;
|
|
|
|
ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf);
|
|
|
|
break;
|
|
|
|
case ISL_AUX_USAGE_CCS_D:
|
|
|
|
case ISL_AUX_USAGE_CCS_E:
|
|
|
|
/* When CCS_E is used, we need to ensure that the CCS starts off in
|
|
|
|
* a valid state. From the Sky Lake PRM, "MCS Buffer for Render
|
|
|
|
* Target(s)":
|
|
|
|
*
|
|
|
|
* "If Software wants to enable Color Compression without Fast
|
|
|
|
* clear, Software needs to initialize MCS with zeros."
|
|
|
|
*
|
|
|
|
* A CCS value of 0 indicates that the corresponding block is in the
|
|
|
|
* pass-through state which is what we want.
|
|
|
|
*
|
|
|
|
* For CCS_D, do the same thing. On Gen9+, this avoids having any
|
|
|
|
* undefined bits in the aux buffer.
|
|
|
|
*/
|
|
|
|
initial_state = ISL_AUX_STATE_PASS_THROUGH;
|
|
|
|
alloc_flags |= BO_ALLOC_ZEROED;
|
|
|
|
ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* No work is needed for a zero-sized auxiliary buffer. */
|
|
|
|
if (res->aux.surf.size_B == 0)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
/* Assert that ISL gave us a valid aux surf */
|
|
|
|
assert(ok);
|
|
|
|
|
|
|
|
/* Create the aux_state for the auxiliary buffer. */
|
|
|
|
res->aux.state = create_aux_state_map(res, initial_state);
|
|
|
|
if (!res->aux.state)
|
|
|
|
return false;
|
|
|
|
|
2019-02-15 22:45:05 +00:00
|
|
|
uint64_t size = res->aux.surf.size_B;
|
|
|
|
|
|
|
|
/* Allocate space in the buffer for storing the clear color. On modern
|
|
|
|
* platforms (gen > 9), we can read it directly from such buffer.
|
|
|
|
*
|
|
|
|
* On gen <= 9, we are going to store the clear color on the buffer
|
|
|
|
* anyways, and copy it back to the surface state during state emission.
|
|
|
|
*/
|
|
|
|
res->aux.clear_color_offset = size;
|
|
|
|
size += clear_color_state_size;
|
|
|
|
|
2018-12-07 19:54:02 +00:00
|
|
|
/* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
|
|
|
|
* the drm allocator. Therefore, one can pass the ISL dimensions in terms
|
|
|
|
* of bytes instead of trying to recalculate based on different format
|
|
|
|
* block sizes.
|
|
|
|
*/
|
2019-02-15 22:45:05 +00:00
|
|
|
res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size,
|
2018-12-07 19:54:02 +00:00
|
|
|
IRIS_MEMZONE_OTHER, I915_TILING_Y,
|
|
|
|
res->aux.surf.row_pitch_B, alloc_flags);
|
2019-02-15 22:16:04 +00:00
|
|
|
if (!res->aux.bo) {
|
2018-12-07 19:54:02 +00:00
|
|
|
return false;
|
2019-02-15 22:16:04 +00:00
|
|
|
}
|
2018-12-07 19:54:02 +00:00
|
|
|
|
2019-02-15 22:45:05 +00:00
|
|
|
if (!(alloc_flags & BO_ALLOC_ZEROED)) {
|
2018-12-07 19:54:02 +00:00
|
|
|
void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
|
2019-02-15 22:45:05 +00:00
|
|
|
|
2019-02-15 22:16:04 +00:00
|
|
|
if (!map) {
|
|
|
|
iris_resource_disable_aux(res);
|
2018-12-07 19:54:02 +00:00
|
|
|
return false;
|
2019-02-15 22:16:04 +00:00
|
|
|
}
|
2018-12-07 19:54:02 +00:00
|
|
|
|
2019-02-15 22:45:05 +00:00
|
|
|
if (memset_value != 0)
|
|
|
|
memset(map, memset_value, res->aux.surf.size_B);
|
|
|
|
|
|
|
|
/* Zero the indirect clear color to match ::fast_clear_color. */
|
|
|
|
memset((char *)map + res->aux.clear_color_offset, 0,
|
|
|
|
clear_color_state_size);
|
|
|
|
|
2018-12-07 19:54:02 +00:00
|
|
|
iris_bo_unmap(res->aux.bo);
|
|
|
|
}
|
|
|
|
|
2019-03-26 23:28:10 +00:00
|
|
|
if (clear_color_state_size > 0) {
|
|
|
|
res->aux.clear_color_bo = res->aux.bo;
|
|
|
|
iris_bo_reference(res->aux.clear_color_bo);
|
|
|
|
}
|
2019-02-15 22:45:05 +00:00
|
|
|
|
2018-12-10 08:35:48 +00:00
|
|
|
if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
|
|
|
|
for (unsigned level = 0; level < res->surf.levels; ++level) {
|
|
|
|
uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
|
|
|
|
uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
|
|
|
|
|
|
|
|
/* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
|
|
|
|
* For LOD == 0, we can grow the dimensions to make it work.
|
|
|
|
*/
|
|
|
|
if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
|
|
|
|
res->aux.has_hiz |= 1 << level;
|
|
|
|
}
|
|
|
|
}
|
2018-12-07 19:54:02 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-12-07 19:02:50 +00:00
|
|
|
static bool
|
|
|
|
supports_mcs(const struct isl_surf *surf)
|
|
|
|
{
|
|
|
|
/* MCS compression only applies to multisampled resources. */
|
|
|
|
if (surf->samples <= 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* See isl_surf_get_mcs_surf for details. */
|
|
|
|
if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Depth and stencil buffers use the IMS (interleaved) layout. */
|
|
|
|
if (isl_surf_usage_is_depth_or_stencil(surf->usage))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
supports_ccs(const struct gen_device_info *devinfo,
|
|
|
|
const struct isl_surf *surf)
|
|
|
|
{
|
|
|
|
/* Gen9+ only supports CCS for Y-tiled buffers. */
|
|
|
|
if (surf->tiling != ISL_TILING_Y0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* CCS only supports singlesampled resources. */
|
|
|
|
if (surf->samples > 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* The PRM doesn't say this explicitly, but fast-clears don't appear to
|
|
|
|
* work for 3D textures until Gen9 where the layout of 3D textures changes
|
|
|
|
* to match 2D array textures.
|
|
|
|
*/
|
|
|
|
if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Note: still need to check the format! */
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-10-25 23:02:56 +01:00
|
|
|
static struct pipe_resource *
|
|
|
|
iris_resource_create_for_buffer(struct pipe_screen *pscreen,
|
|
|
|
const struct pipe_resource *templ)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
|
|
|
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
|
|
|
|
|
|
|
|
assert(templ->target == PIPE_BUFFER);
|
|
|
|
assert(templ->height0 <= 1);
|
|
|
|
assert(templ->depth0 <= 1);
|
|
|
|
assert(templ->format == PIPE_FORMAT_NONE ||
|
|
|
|
util_format_get_blocksize(templ->format) == 1);
|
|
|
|
|
|
|
|
res->internal_format = templ->format;
|
|
|
|
res->surf.tiling = ISL_TILING_LINEAR;
|
|
|
|
|
|
|
|
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
|
|
|
|
const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree";
|
|
|
|
if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) {
|
|
|
|
memzone = IRIS_MEMZONE_SHADER;
|
|
|
|
name = "shader kernels";
|
|
|
|
} else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) {
|
|
|
|
memzone = IRIS_MEMZONE_SURFACE;
|
|
|
|
name = "surface state";
|
|
|
|
} else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) {
|
|
|
|
memzone = IRIS_MEMZONE_DYNAMIC;
|
|
|
|
name = "dynamic state";
|
|
|
|
}
|
|
|
|
|
|
|
|
res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone);
|
|
|
|
if (!res->bo) {
|
|
|
|
iris_resource_destroy(pscreen, &res->base);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &res->base;
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
static struct pipe_resource *
|
|
|
|
iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
|
|
|
|
const struct pipe_resource *templ,
|
|
|
|
const uint64_t *modifiers,
|
|
|
|
int modifiers_count)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
|
|
|
struct gen_device_info *devinfo = &screen->devinfo;
|
|
|
|
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
|
2018-07-30 23:08:02 +01:00
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
if (!res)
|
|
|
|
return NULL;
|
|
|
|
|
2018-12-07 19:02:50 +00:00
|
|
|
const struct util_format_description *format_desc =
|
|
|
|
util_format_description(templ->format);
|
2018-07-30 23:08:02 +01:00
|
|
|
const bool has_depth = util_format_has_depth(format_desc);
|
2018-11-28 10:30:42 +00:00
|
|
|
uint64_t modifier =
|
|
|
|
select_best_modifier(devinfo, modifiers, modifiers_count);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-11-28 10:30:42 +00:00
|
|
|
isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-11-28 10:30:42 +00:00
|
|
|
if (modifier != DRM_FORMAT_MOD_INVALID) {
|
2018-12-09 20:11:17 +00:00
|
|
|
res->mod_info = isl_drm_modifier_get_info(modifier);
|
2018-01-19 23:09:05 +00:00
|
|
|
|
2018-12-09 20:11:17 +00:00
|
|
|
tiling_flags = 1 << res->mod_info->tiling;
|
2018-11-28 10:30:42 +00:00
|
|
|
} else {
|
|
|
|
if (modifiers_count > 0) {
|
|
|
|
fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
|
2017-11-24 07:15:14 +00:00
|
|
|
return NULL;
|
2018-11-28 10:30:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* No modifiers - we can select our own tiling. */
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-11-28 10:30:42 +00:00
|
|
|
if (has_depth) {
|
|
|
|
/* Depth must be Y-tiled */
|
|
|
|
tiling_flags = ISL_TILING_Y0_BIT;
|
|
|
|
} else if (templ->format == PIPE_FORMAT_S8_UINT) {
|
|
|
|
/* Stencil must be W-tiled */
|
|
|
|
tiling_flags = ISL_TILING_W_BIT;
|
|
|
|
} else if (templ->target == PIPE_BUFFER ||
|
|
|
|
templ->target == PIPE_TEXTURE_1D ||
|
|
|
|
templ->target == PIPE_TEXTURE_1D_ARRAY) {
|
|
|
|
/* Use linear for buffers and 1D textures */
|
|
|
|
tiling_flags = ISL_TILING_LINEAR_BIT;
|
|
|
|
}
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-11-28 10:30:42 +00:00
|
|
|
/* Use linear for staging buffers */
|
|
|
|
if (templ->usage == PIPE_USAGE_STAGING ||
|
|
|
|
templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) )
|
|
|
|
tiling_flags = ISL_TILING_LINEAR_BIT;
|
|
|
|
}
|
2018-07-30 23:08:02 +01:00
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
|
|
|
|
|
2018-07-28 04:25:21 +01:00
|
|
|
if (templ->target == PIPE_TEXTURE_CUBE ||
|
|
|
|
templ->target == PIPE_TEXTURE_CUBE_ARRAY)
|
2017-11-24 07:15:14 +00:00
|
|
|
usage |= ISL_SURF_USAGE_CUBE_BIT;
|
|
|
|
|
2018-07-30 23:08:02 +01:00
|
|
|
if (templ->usage != PIPE_USAGE_STAGING) {
|
|
|
|
if (templ->format == PIPE_FORMAT_S8_UINT)
|
|
|
|
usage |= ISL_SURF_USAGE_STENCIL_BIT;
|
|
|
|
else if (has_depth)
|
|
|
|
usage |= ISL_SURF_USAGE_DEPTH_BIT;
|
|
|
|
}
|
2018-04-25 23:25:33 +01:00
|
|
|
|
2018-08-03 09:24:51 +01:00
|
|
|
enum pipe_format pfmt = templ->format;
|
2018-08-08 22:54:09 +01:00
|
|
|
res->internal_format = pfmt;
|
2018-08-03 09:24:51 +01:00
|
|
|
|
2018-08-09 11:28:24 +01:00
|
|
|
/* Should be handled by u_transfer_helper */
|
|
|
|
assert(!util_format_is_depth_and_stencil(pfmt));
|
2018-04-25 23:25:33 +01:00
|
|
|
|
2018-10-08 04:31:09 +01:00
|
|
|
struct iris_format_info fmt = iris_format_for_usage(devinfo, pfmt, usage);
|
|
|
|
assert(fmt.fmt != ISL_FORMAT_UNSUPPORTED);
|
2018-04-25 23:25:33 +01:00
|
|
|
|
2018-04-25 07:38:10 +01:00
|
|
|
UNUSED const bool isl_surf_created_successfully =
|
|
|
|
isl_surf_init(&screen->isl_dev, &res->surf,
|
|
|
|
.dim = target_to_isl_surf_dim(templ->target),
|
2018-10-08 04:31:09 +01:00
|
|
|
.format = fmt.fmt,
|
2018-04-25 07:38:10 +01:00
|
|
|
.width = templ->width0,
|
|
|
|
.height = templ->height0,
|
|
|
|
.depth = templ->depth0,
|
|
|
|
.levels = templ->last_level + 1,
|
|
|
|
.array_len = templ->array_size,
|
|
|
|
.samples = MAX2(templ->nr_samples, 1),
|
|
|
|
.min_alignment_B = 0,
|
|
|
|
.row_pitch_B = 0,
|
|
|
|
.usage = usage,
|
2018-11-28 10:30:42 +00:00
|
|
|
.tiling_flags = tiling_flags);
|
2018-04-25 07:38:10 +01:00
|
|
|
assert(isl_surf_created_successfully);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-12-09 20:11:17 +00:00
|
|
|
if (res->mod_info) {
|
|
|
|
res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
|
2019-03-13 23:56:55 +00:00
|
|
|
} else if (supports_mcs(&res->surf)) {
|
|
|
|
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS;
|
|
|
|
} else if (has_depth) {
|
|
|
|
if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ)))
|
|
|
|
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
|
|
|
|
} else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) &&
|
|
|
|
supports_ccs(devinfo, &res->surf)) {
|
|
|
|
if (isl_format_supports_ccs_e(devinfo, res->surf.format))
|
|
|
|
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
|
|
|
|
|
|
|
|
if (isl_format_supports_ccs_d(devinfo, res->surf.format))
|
|
|
|
res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
|
2018-12-07 19:02:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
|
|
|
|
|
2019-03-27 21:42:12 +00:00
|
|
|
res->aux.sampler_usages = res->aux.possible_usages;
|
|
|
|
|
|
|
|
/* We don't always support sampling with hiz. But when we do, it must be
|
|
|
|
* single sampled.
|
|
|
|
*/
|
|
|
|
if (!devinfo->has_sample_with_hiz || res->surf.samples > 1) {
|
|
|
|
res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ);
|
|
|
|
}
|
|
|
|
|
2018-12-07 19:02:50 +00:00
|
|
|
const char *name = "miptree";
|
2018-04-03 09:40:23 +01:00
|
|
|
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
|
2018-10-25 23:02:56 +01:00
|
|
|
|
2019-02-22 21:24:46 +00:00
|
|
|
unsigned int flags = 0;
|
|
|
|
if (templ->usage == PIPE_USAGE_STAGING)
|
|
|
|
flags |= BO_ALLOC_COHERENT;
|
|
|
|
|
2018-10-25 23:02:56 +01:00
|
|
|
/* These are for u_upload_mgr buffers only */
|
|
|
|
assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
|
|
|
|
IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
|
|
|
|
IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE)));
|
2018-04-03 09:40:23 +01:00
|
|
|
|
|
|
|
res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B,
|
2018-04-05 22:52:53 +01:00
|
|
|
memzone,
|
2017-11-24 07:15:14 +00:00
|
|
|
isl_tiling_to_i915_tiling(res->surf.tiling),
|
2019-02-22 21:24:46 +00:00
|
|
|
res->surf.row_pitch_B, flags);
|
2018-12-07 19:54:02 +00:00
|
|
|
|
|
|
|
if (!res->bo)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
if (!iris_resource_alloc_aux(screen, res))
|
|
|
|
goto fail;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
return &res->base;
|
2018-12-07 19:54:02 +00:00
|
|
|
|
|
|
|
fail:
|
|
|
|
fprintf(stderr, "XXX: resource creation failed\n");
|
|
|
|
iris_resource_destroy(pscreen, &res->base);
|
|
|
|
return NULL;
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct pipe_resource *
|
|
|
|
iris_resource_create(struct pipe_screen *pscreen,
|
|
|
|
const struct pipe_resource *templ)
|
|
|
|
{
|
2018-10-25 23:02:56 +01:00
|
|
|
if (templ->target == PIPE_BUFFER)
|
|
|
|
return iris_resource_create_for_buffer(pscreen, templ);
|
|
|
|
else
|
|
|
|
return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0);
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
|
2018-06-02 12:32:19 +01:00
|
|
|
static uint64_t
|
|
|
|
tiling_to_modifier(uint32_t tiling)
|
|
|
|
{
|
|
|
|
static const uint64_t map[] = {
|
|
|
|
[I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR,
|
|
|
|
[I915_TILING_X] = I915_FORMAT_MOD_X_TILED,
|
|
|
|
[I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED,
|
|
|
|
};
|
|
|
|
|
|
|
|
assert(tiling < ARRAY_SIZE(map));
|
|
|
|
|
|
|
|
return map[tiling];
|
|
|
|
}
|
|
|
|
|
2018-07-31 14:47:02 +01:00
|
|
|
static struct pipe_resource *
|
|
|
|
iris_resource_from_user_memory(struct pipe_screen *pscreen,
|
|
|
|
const struct pipe_resource *templ,
|
|
|
|
void *user_memory)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
|
|
|
struct iris_bufmgr *bufmgr = screen->bufmgr;
|
|
|
|
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
|
|
|
|
if (!res)
|
|
|
|
return NULL;
|
|
|
|
|
2018-10-25 23:02:56 +01:00
|
|
|
assert(templ->target == PIPE_BUFFER);
|
|
|
|
|
|
|
|
res->internal_format = templ->format;
|
2018-07-31 14:47:02 +01:00
|
|
|
res->bo = iris_bo_create_userptr(bufmgr, "user",
|
|
|
|
user_memory, templ->width0,
|
|
|
|
IRIS_MEMZONE_OTHER);
|
|
|
|
if (!res->bo) {
|
|
|
|
free(res);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &res->base;
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
static struct pipe_resource *
|
|
|
|
iris_resource_from_handle(struct pipe_screen *pscreen,
|
|
|
|
const struct pipe_resource *templ,
|
|
|
|
struct winsys_handle *whandle,
|
|
|
|
unsigned usage)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
2018-10-08 04:31:09 +01:00
|
|
|
struct gen_device_info *devinfo = &screen->devinfo;
|
2017-11-24 07:15:14 +00:00
|
|
|
struct iris_bufmgr *bufmgr = screen->bufmgr;
|
|
|
|
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
|
|
|
|
if (!res)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (whandle->offset != 0) {
|
|
|
|
dbg_printf("Attempt to import unsupported winsys offset %u\n",
|
|
|
|
whandle->offset);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (whandle->type) {
|
2018-06-02 12:32:19 +01:00
|
|
|
case WINSYS_HANDLE_TYPE_FD:
|
2017-11-24 07:15:14 +00:00
|
|
|
res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
|
|
|
|
break;
|
2018-06-02 12:32:19 +01:00
|
|
|
case WINSYS_HANDLE_TYPE_SHARED:
|
2017-11-24 07:15:14 +00:00
|
|
|
res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
|
|
|
|
whandle->handle);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("invalid winsys handle type");
|
|
|
|
}
|
2018-06-02 12:32:19 +01:00
|
|
|
if (!res->bo)
|
2018-07-31 07:49:34 +01:00
|
|
|
return NULL;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-06-02 12:32:19 +01:00
|
|
|
uint64_t modifier = whandle->modifier;
|
|
|
|
if (modifier == DRM_FORMAT_MOD_INVALID) {
|
2018-12-10 08:49:35 +00:00
|
|
|
modifier = tiling_to_modifier(res->bo->tiling_mode);
|
2018-06-02 12:32:19 +01:00
|
|
|
}
|
2018-12-09 20:11:17 +00:00
|
|
|
res->mod_info = isl_drm_modifier_get_info(modifier);
|
|
|
|
assert(res->mod_info);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-12-17 06:25:11 +00:00
|
|
|
isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-10-08 04:31:09 +01:00
|
|
|
const struct iris_format_info fmt =
|
|
|
|
iris_format_for_usage(devinfo, templ->format, isl_usage);
|
2019-02-13 21:07:51 +00:00
|
|
|
res->internal_format = templ->format;
|
2018-10-08 04:31:09 +01:00
|
|
|
|
2018-10-25 23:02:56 +01:00
|
|
|
if (templ->target == PIPE_BUFFER) {
|
|
|
|
res->surf.tiling = ISL_TILING_LINEAR;
|
|
|
|
} else {
|
|
|
|
isl_surf_init(&screen->isl_dev, &res->surf,
|
|
|
|
.dim = target_to_isl_surf_dim(templ->target),
|
|
|
|
.format = fmt.fmt,
|
|
|
|
.width = templ->width0,
|
|
|
|
.height = templ->height0,
|
|
|
|
.depth = templ->depth0,
|
|
|
|
.levels = templ->last_level + 1,
|
|
|
|
.array_len = templ->array_size,
|
|
|
|
.samples = MAX2(templ->nr_samples, 1),
|
|
|
|
.min_alignment_B = 0,
|
2018-12-02 21:37:55 +00:00
|
|
|
.row_pitch_B = whandle->stride,
|
2018-10-25 23:02:56 +01:00
|
|
|
.usage = isl_usage,
|
2018-12-09 20:11:17 +00:00
|
|
|
.tiling_flags = 1 << res->mod_info->tiling);
|
2018-10-25 23:02:56 +01:00
|
|
|
|
|
|
|
assert(res->bo->tiling_mode ==
|
|
|
|
isl_tiling_to_i915_tiling(res->surf.tiling));
|
2018-12-07 19:54:02 +00:00
|
|
|
|
|
|
|
// XXX: create_ccs_buf_for_image?
|
|
|
|
if (!iris_resource_alloc_aux(screen, res))
|
|
|
|
goto fail;
|
2018-10-25 23:02:56 +01:00
|
|
|
}
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
return &res->base;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
iris_resource_destroy(pscreen, &res->base);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-03-28 08:49:45 +00:00
|
|
|
static void
|
|
|
|
iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
|
|
|
|
{
|
|
|
|
struct iris_context *ice = (struct iris_context *)ctx;
|
|
|
|
struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
|
|
|
|
struct iris_resource *res = (void *) resource;
|
|
|
|
const struct isl_drm_modifier_info *mod = res->mod_info;
|
|
|
|
|
|
|
|
iris_resource_prepare_access(ice, render_batch, res,
|
|
|
|
0, INTEL_REMAINING_LEVELS,
|
|
|
|
0, INTEL_REMAINING_LAYERS,
|
|
|
|
mod ? mod->aux_usage : ISL_AUX_USAGE_NONE,
|
|
|
|
mod ? mod->supports_clear_color : false);
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
static boolean
|
|
|
|
iris_resource_get_handle(struct pipe_screen *pscreen,
|
|
|
|
struct pipe_context *ctx,
|
|
|
|
struct pipe_resource *resource,
|
|
|
|
struct winsys_handle *whandle,
|
|
|
|
unsigned usage)
|
|
|
|
{
|
|
|
|
struct iris_resource *res = (struct iris_resource *)resource;
|
|
|
|
|
2019-04-05 06:55:18 +01:00
|
|
|
/* Disable aux usage if explicit flush not set and this is the
|
|
|
|
* first time we are dealing with this resource.
|
|
|
|
*/
|
|
|
|
if ((!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0)) {
|
|
|
|
if (p_atomic_read(&resource->reference.count) == 1)
|
|
|
|
iris_resource_disable_aux(res);
|
|
|
|
}
|
|
|
|
|
2018-10-25 23:02:56 +01:00
|
|
|
/* If this is a buffer, stride should be 0 - no need to special case */
|
2017-11-24 07:15:14 +00:00
|
|
|
whandle->stride = res->surf.row_pitch_B;
|
2018-12-10 07:12:33 +00:00
|
|
|
whandle->modifier =
|
|
|
|
res->mod_info ? res->mod_info->modifier
|
|
|
|
: tiling_to_modifier(res->bo->tiling_mode);
|
|
|
|
|
2019-02-28 19:08:32 +00:00
|
|
|
#ifndef NDEBUG
|
|
|
|
enum isl_aux_usage allowed_usage =
|
|
|
|
res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
|
|
|
|
|
|
|
|
if (res->aux.usage != allowed_usage) {
|
|
|
|
enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
|
|
|
|
assert(aux_state == ISL_AUX_STATE_RESOLVED ||
|
|
|
|
aux_state == ISL_AUX_STATE_PASS_THROUGH);
|
2018-12-10 07:12:33 +00:00
|
|
|
}
|
2019-02-28 19:08:32 +00:00
|
|
|
#endif
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
switch (whandle->type) {
|
|
|
|
case WINSYS_HANDLE_TYPE_SHARED:
|
2018-01-30 20:30:34 +00:00
|
|
|
return iris_bo_flink(res->bo, &whandle->handle) == 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
case WINSYS_HANDLE_TYPE_KMS:
|
2018-11-13 17:55:45 +00:00
|
|
|
whandle->handle = iris_bo_export_gem_handle(res->bo);
|
|
|
|
return true;
|
2017-11-24 07:15:14 +00:00
|
|
|
case WINSYS_HANDLE_TYPE_FD:
|
2018-01-30 20:30:34 +00:00
|
|
|
return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-12-21 11:04:18 +00:00
|
|
|
static void
|
2019-04-07 07:35:49 +01:00
|
|
|
iris_flush_staging_region(struct pipe_transfer *xfer,
|
|
|
|
const struct pipe_box *flush_box)
|
2018-12-21 11:04:18 +00:00
|
|
|
{
|
2019-04-07 07:35:49 +01:00
|
|
|
if (!(xfer->usage & PIPE_TRANSFER_WRITE))
|
|
|
|
return;
|
|
|
|
|
|
|
|
struct iris_transfer *map = (void *) xfer;
|
|
|
|
|
|
|
|
struct pipe_box src_box = *flush_box;
|
|
|
|
|
|
|
|
/* Account for extra alignment padding in staging buffer */
|
|
|
|
if (xfer->resource->target == PIPE_BUFFER)
|
|
|
|
src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT;
|
|
|
|
|
|
|
|
struct pipe_box dst_box = (struct pipe_box) {
|
|
|
|
.x = xfer->box.x + flush_box->x,
|
|
|
|
.y = xfer->box.y + flush_box->y,
|
|
|
|
.z = xfer->box.z + flush_box->z,
|
|
|
|
.width = flush_box->width,
|
|
|
|
.height = flush_box->height,
|
|
|
|
.depth = flush_box->depth,
|
2018-12-21 11:04:18 +00:00
|
|
|
};
|
|
|
|
|
2019-04-07 07:35:49 +01:00
|
|
|
iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level,
|
|
|
|
dst_box.x, dst_box.y, dst_box.z, map->staging, 0,
|
|
|
|
&src_box);
|
|
|
|
}
|
2018-12-21 11:04:18 +00:00
|
|
|
|
2019-04-07 07:35:49 +01:00
|
|
|
static void
|
|
|
|
iris_unmap_copy_region(struct iris_transfer *map)
|
|
|
|
{
|
2018-12-21 11:04:18 +00:00
|
|
|
iris_resource_destroy(map->staging->screen, map->staging);
|
|
|
|
|
|
|
|
map->ptr = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_map_copy_region(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_screen *pscreen = &map->batch->screen->base;
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
|
|
|
struct pipe_box *box = &xfer->box;
|
|
|
|
struct iris_resource *res = (void *) xfer->resource;
|
|
|
|
|
|
|
|
unsigned extra = xfer->resource->target == PIPE_BUFFER ?
|
|
|
|
box->x % IRIS_MAP_BUFFER_ALIGNMENT : 0;
|
|
|
|
|
|
|
|
struct pipe_resource templ = (struct pipe_resource) {
|
|
|
|
.usage = PIPE_USAGE_STAGING,
|
|
|
|
.width0 = box->width + extra,
|
|
|
|
.height0 = box->height,
|
|
|
|
.depth0 = 1,
|
|
|
|
.nr_samples = xfer->resource->nr_samples,
|
|
|
|
.nr_storage_samples = xfer->resource->nr_storage_samples,
|
|
|
|
.array_size = box->depth,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (xfer->resource->target == PIPE_BUFFER)
|
|
|
|
templ.target = PIPE_BUFFER;
|
|
|
|
else if (templ.array_size > 1)
|
|
|
|
templ.target = PIPE_TEXTURE_2D_ARRAY;
|
|
|
|
else
|
|
|
|
templ.target = PIPE_TEXTURE_2D;
|
|
|
|
|
|
|
|
/* Depth, stencil, and ASTC can't be linear surfaces, so we can't use
|
|
|
|
* xfer->resource->format directly. Pick a bpb compatible format so
|
|
|
|
* resource creation will succeed; blorp_copy will override it anyway.
|
|
|
|
*/
|
|
|
|
switch (util_format_get_blocksizebits(res->internal_format)) {
|
|
|
|
case 8: templ.format = PIPE_FORMAT_R8_UINT; break;
|
|
|
|
case 16: templ.format = PIPE_FORMAT_R8G8_UINT; break;
|
|
|
|
case 24: templ.format = PIPE_FORMAT_R8G8B8_UINT; break;
|
|
|
|
case 32: templ.format = PIPE_FORMAT_R8G8B8A8_UINT; break;
|
|
|
|
case 48: templ.format = PIPE_FORMAT_R16G16B16_UINT; break;
|
|
|
|
case 64: templ.format = PIPE_FORMAT_R16G16B16A16_UINT; break;
|
|
|
|
case 96: templ.format = PIPE_FORMAT_R32G32B32_UINT; break;
|
|
|
|
case 128: templ.format = PIPE_FORMAT_R32G32B32A32_UINT; break;
|
|
|
|
default: unreachable("Invalid bpb");
|
|
|
|
}
|
|
|
|
|
|
|
|
map->staging = iris_resource_create(pscreen, &templ);
|
|
|
|
assert(map->staging);
|
|
|
|
|
|
|
|
if (templ.target != PIPE_BUFFER) {
|
|
|
|
struct isl_surf *surf = &((struct iris_resource *) map->staging)->surf;
|
|
|
|
xfer->stride = isl_surf_get_row_pitch_B(surf);
|
|
|
|
xfer->layer_stride = isl_surf_get_array_pitch(surf);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
|
|
|
|
iris_copy_region(map->blorp, map->batch, map->staging, 0, extra, 0, 0,
|
|
|
|
xfer->resource, xfer->level, box);
|
|
|
|
/* Ensure writes to the staging BO land before we map it below. */
|
|
|
|
iris_emit_pipe_control_flush(map->batch,
|
|
|
|
PIPE_CONTROL_RENDER_TARGET_FLUSH |
|
|
|
|
PIPE_CONTROL_CS_STALL);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct iris_bo *staging_bo = iris_resource_bo(map->staging);
|
|
|
|
|
|
|
|
if (iris_batch_references(map->batch, staging_bo))
|
|
|
|
iris_batch_flush(map->batch);
|
|
|
|
|
2019-04-08 08:45:41 +01:00
|
|
|
map->ptr =
|
|
|
|
iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra;
|
2018-12-21 11:04:18 +00:00
|
|
|
|
|
|
|
map->unmap = iris_unmap_copy_region;
|
|
|
|
}
|
|
|
|
|
2018-08-07 17:21:40 +01:00
|
|
|
static void
|
|
|
|
get_image_offset_el(struct isl_surf *surf, unsigned level, unsigned z,
|
|
|
|
unsigned *out_x0_el, unsigned *out_y0_el)
|
|
|
|
{
|
|
|
|
if (surf->dim == ISL_SURF_DIM_3D) {
|
|
|
|
isl_surf_get_image_offset_el(surf, level, 0, z, out_x0_el, out_y0_el);
|
|
|
|
} else {
|
|
|
|
isl_surf_get_image_offset_el(surf, level, z, 0, out_x0_el, out_y0_el);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Get pointer offset into stencil buffer.
|
|
|
|
*
|
|
|
|
* The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
|
|
|
|
* must decode the tile's layout in software.
|
|
|
|
*
|
|
|
|
* See
|
|
|
|
* - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
|
|
|
|
* Format.
|
|
|
|
* - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
|
|
|
|
*
|
|
|
|
* Even though the returned offset is always positive, the return type is
|
|
|
|
* signed due to
|
|
|
|
* commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
|
|
|
|
* mesa: Fix return type of _mesa_get_format_bytes() (#37351)
|
|
|
|
*/
|
|
|
|
static intptr_t
|
|
|
|
s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
|
|
|
|
{
|
|
|
|
uint32_t tile_size = 4096;
|
|
|
|
uint32_t tile_width = 64;
|
|
|
|
uint32_t tile_height = 64;
|
|
|
|
uint32_t row_size = 64 * stride / 2; /* Two rows are interleaved. */
|
|
|
|
|
|
|
|
uint32_t tile_x = x / tile_width;
|
|
|
|
uint32_t tile_y = y / tile_height;
|
|
|
|
|
|
|
|
/* The byte's address relative to the tile's base addres. */
|
|
|
|
uint32_t byte_x = x % tile_width;
|
|
|
|
uint32_t byte_y = y % tile_height;
|
|
|
|
|
|
|
|
uintptr_t u = tile_y * row_size
|
|
|
|
+ tile_x * tile_size
|
|
|
|
+ 512 * (byte_x / 8)
|
|
|
|
+ 64 * (byte_y / 8)
|
|
|
|
+ 32 * ((byte_y / 4) % 2)
|
|
|
|
+ 16 * ((byte_x / 4) % 2)
|
|
|
|
+ 8 * ((byte_y / 2) % 2)
|
|
|
|
+ 4 * ((byte_x / 2) % 2)
|
|
|
|
+ 2 * (byte_y % 2)
|
|
|
|
+ 1 * (byte_x % 2);
|
|
|
|
|
|
|
|
if (swizzled) {
|
|
|
|
/* adjust for bit6 swizzling */
|
|
|
|
if (((byte_x / 8) % 2) == 1) {
|
2018-12-10 08:49:35 +00:00
|
|
|
if (((byte_y / 8) % 2) == 0) {
|
|
|
|
u += 64;
|
|
|
|
} else {
|
|
|
|
u -= 64;
|
|
|
|
}
|
2018-08-07 17:21:40 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return u;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_unmap_s8(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
2019-03-13 22:35:28 +00:00
|
|
|
const struct pipe_box *box = &xfer->box;
|
2018-08-07 17:21:40 +01:00
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
|
|
|
struct isl_surf *surf = &res->surf;
|
2018-10-16 03:25:24 +01:00
|
|
|
const bool has_swizzling = false;
|
2018-08-07 17:21:40 +01:00
|
|
|
|
|
|
|
if (xfer->usage & PIPE_TRANSFER_WRITE) {
|
|
|
|
uint8_t *untiled_s8_map = map->ptr;
|
|
|
|
uint8_t *tiled_s8_map =
|
2019-04-08 08:45:41 +01:00
|
|
|
iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
|
2018-08-07 17:21:40 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (int s = 0; s < box->depth; s++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
unsigned x0_el, y0_el;
|
2019-03-13 22:35:28 +00:00
|
|
|
get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
|
2018-08-07 17:21:40 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (uint32_t y = 0; y < box->height; y++) {
|
|
|
|
for (uint32_t x = 0; x < box->width; x++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
|
2019-03-13 22:35:28 +00:00
|
|
|
x0_el + box->x + x,
|
|
|
|
y0_el + box->y + y,
|
2018-08-07 17:21:40 +01:00
|
|
|
has_swizzling);
|
|
|
|
tiled_s8_map[offset] =
|
|
|
|
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
free(map->buffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_map_s8(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
2019-03-13 22:35:28 +00:00
|
|
|
const struct pipe_box *box = &xfer->box;
|
2018-08-07 17:21:40 +01:00
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
|
|
|
struct isl_surf *surf = &res->surf;
|
|
|
|
|
|
|
|
xfer->stride = surf->row_pitch_B;
|
2019-03-13 22:35:28 +00:00
|
|
|
xfer->layer_stride = xfer->stride * box->height;
|
2018-08-07 17:21:40 +01:00
|
|
|
|
|
|
|
/* The tiling and detiling functions require that the linear buffer has
|
|
|
|
* a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
|
|
|
|
* over-allocate the linear buffer to get the proper alignment.
|
|
|
|
*/
|
2019-03-13 22:35:28 +00:00
|
|
|
map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth);
|
2018-08-07 17:21:40 +01:00
|
|
|
assert(map->buffer);
|
|
|
|
|
2018-10-16 03:25:24 +01:00
|
|
|
const bool has_swizzling = false;
|
2018-08-07 17:21:40 +01:00
|
|
|
|
|
|
|
/* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
|
|
|
|
* INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
|
|
|
|
* invalidate is set, since we'll be writing the whole rectangle from our
|
|
|
|
* temporary buffer back out.
|
|
|
|
*/
|
|
|
|
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
|
|
|
|
uint8_t *untiled_s8_map = map->ptr;
|
|
|
|
uint8_t *tiled_s8_map =
|
2019-04-08 08:45:41 +01:00
|
|
|
iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
|
2018-08-07 17:21:40 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (int s = 0; s < box->depth; s++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
unsigned x0_el, y0_el;
|
2019-03-13 22:35:28 +00:00
|
|
|
get_image_offset_el(surf, xfer->level, box->z + s, &x0_el, &y0_el);
|
2018-08-07 17:21:40 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (uint32_t y = 0; y < box->height; y++) {
|
|
|
|
for (uint32_t x = 0; x < box->width; x++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
ptrdiff_t offset = s8_offset(surf->row_pitch_B,
|
2019-03-13 22:35:28 +00:00
|
|
|
x0_el + box->x + x,
|
|
|
|
y0_el + box->y + y,
|
2018-08-07 17:21:40 +01:00
|
|
|
has_swizzling);
|
|
|
|
untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] =
|
|
|
|
tiled_s8_map[offset];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
map->unmap = iris_unmap_s8;
|
|
|
|
}
|
|
|
|
|
2018-05-29 01:14:43 +01:00
|
|
|
/* Compute extent parameters for use with tiled_memcpy functions.
|
|
|
|
* xs are in units of bytes and ys are in units of strides.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
tile_extents(struct isl_surf *surf,
|
|
|
|
const struct pipe_box *box,
|
2019-03-13 22:35:28 +00:00
|
|
|
unsigned level, int z,
|
2018-08-07 17:21:40 +01:00
|
|
|
unsigned *x1_B, unsigned *x2_B,
|
|
|
|
unsigned *y1_el, unsigned *y2_el)
|
2018-05-29 01:14:43 +01:00
|
|
|
{
|
|
|
|
const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
|
|
|
|
const unsigned cpp = fmtl->bpb / 8;
|
|
|
|
|
|
|
|
assert(box->x % fmtl->bw == 0);
|
|
|
|
assert(box->y % fmtl->bh == 0);
|
|
|
|
|
|
|
|
unsigned x0_el, y0_el;
|
2019-03-13 22:35:28 +00:00
|
|
|
get_image_offset_el(surf, level, box->z + z, &x0_el, &y0_el);
|
2018-05-29 01:14:43 +01:00
|
|
|
|
|
|
|
*x1_B = (box->x / fmtl->bw + x0_el) * cpp;
|
|
|
|
*y1_el = box->y / fmtl->bh + y0_el;
|
|
|
|
*x2_B = (DIV_ROUND_UP(box->x + box->width, fmtl->bw) + x0_el) * cpp;
|
|
|
|
*y2_el = DIV_ROUND_UP(box->y + box->height, fmtl->bh) + y0_el;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_unmap_tiled_memcpy(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
2019-03-13 22:35:28 +00:00
|
|
|
const struct pipe_box *box = &xfer->box;
|
2018-05-29 01:14:43 +01:00
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
|
|
|
struct isl_surf *surf = &res->surf;
|
|
|
|
|
2018-10-16 03:25:24 +01:00
|
|
|
const bool has_swizzling = false;
|
2018-05-29 01:14:43 +01:00
|
|
|
|
|
|
|
if (xfer->usage & PIPE_TRANSFER_WRITE) {
|
2019-04-08 08:45:41 +01:00
|
|
|
char *dst =
|
|
|
|
iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
|
2018-05-29 01:14:43 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (int s = 0; s < box->depth; s++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
unsigned x1, x2, y1, y2;
|
2019-03-13 22:35:28 +00:00
|
|
|
tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
|
2018-07-12 22:44:55 +01:00
|
|
|
|
2018-08-15 00:44:07 +01:00
|
|
|
void *ptr = map->ptr + s * xfer->layer_stride;
|
2018-07-12 22:44:55 +01:00
|
|
|
|
|
|
|
isl_memcpy_linear_to_tiled(x1, x2, y1, y2, dst, ptr,
|
|
|
|
surf->row_pitch_B, xfer->stride,
|
|
|
|
has_swizzling, surf->tiling, ISL_MEMCPY);
|
|
|
|
}
|
2018-05-29 01:14:43 +01:00
|
|
|
}
|
|
|
|
os_free_aligned(map->buffer);
|
|
|
|
map->buffer = map->ptr = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_map_tiled_memcpy(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
2019-03-13 22:35:28 +00:00
|
|
|
const struct pipe_box *box = &xfer->box;
|
2018-05-29 01:14:43 +01:00
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
|
|
|
struct isl_surf *surf = &res->surf;
|
|
|
|
|
2018-07-12 22:44:55 +01:00
|
|
|
xfer->stride = ALIGN(surf->row_pitch_B, 16);
|
2019-03-13 22:35:28 +00:00
|
|
|
xfer->layer_stride = xfer->stride * box->height;
|
2018-07-12 22:44:55 +01:00
|
|
|
|
2018-06-24 08:27:58 +01:00
|
|
|
unsigned x1, x2, y1, y2;
|
2019-03-13 22:35:28 +00:00
|
|
|
tile_extents(surf, box, xfer->level, 0, &x1, &x2, &y1, &y2);
|
2018-05-29 01:14:43 +01:00
|
|
|
|
|
|
|
/* The tiling and detiling functions require that the linear buffer has
|
|
|
|
* a 16-byte alignment (that is, its `x0` is 16-byte aligned). Here we
|
|
|
|
* over-allocate the linear buffer to get the proper alignment.
|
|
|
|
*/
|
2018-07-04 07:44:40 +01:00
|
|
|
map->buffer =
|
2019-03-13 22:35:28 +00:00
|
|
|
os_malloc_aligned(xfer->layer_stride * box->depth, 16);
|
2018-05-29 01:14:43 +01:00
|
|
|
assert(map->buffer);
|
2018-07-12 22:44:55 +01:00
|
|
|
map->ptr = (char *)map->buffer + (x1 & 0xf);
|
2018-05-29 01:14:43 +01:00
|
|
|
|
2018-10-16 03:25:24 +01:00
|
|
|
const bool has_swizzling = false;
|
2018-05-29 01:14:43 +01:00
|
|
|
|
|
|
|
// XXX: PIPE_TRANSFER_READ?
|
|
|
|
if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) {
|
2019-04-08 08:45:41 +01:00
|
|
|
char *src =
|
|
|
|
iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
|
2018-05-29 01:14:43 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
for (int s = 0; s < box->depth; s++) {
|
2018-08-07 17:21:40 +01:00
|
|
|
unsigned x1, x2, y1, y2;
|
2019-03-13 22:35:28 +00:00
|
|
|
tile_extents(surf, box, xfer->level, s, &x1, &x2, &y1, &y2);
|
2018-07-12 22:44:55 +01:00
|
|
|
|
2019-03-13 22:35:28 +00:00
|
|
|
/* Use 's' rather than 'box->z' to rebase the first slice to 0. */
|
2018-08-15 00:44:07 +01:00
|
|
|
void *ptr = map->ptr + s * xfer->layer_stride;
|
|
|
|
|
|
|
|
isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride,
|
|
|
|
surf->row_pitch_B, has_swizzling,
|
2019-02-22 20:53:41 +00:00
|
|
|
surf->tiling, ISL_MEMCPY_STREAMING_LOAD);
|
2018-07-12 22:44:55 +01:00
|
|
|
}
|
2018-05-29 01:14:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
map->unmap = iris_unmap_tiled_memcpy;
|
|
|
|
}
|
|
|
|
|
2018-06-24 08:27:58 +01:00
|
|
|
static void
|
|
|
|
iris_map_direct(struct iris_transfer *map)
|
|
|
|
{
|
|
|
|
struct pipe_transfer *xfer = &map->base;
|
|
|
|
struct pipe_box *box = &xfer->box;
|
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
2018-08-23 10:36:18 +01:00
|
|
|
|
2019-04-08 08:45:41 +01:00
|
|
|
void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
|
2018-06-24 08:27:58 +01:00
|
|
|
|
2018-11-10 10:25:24 +00:00
|
|
|
if (res->base.target == PIPE_BUFFER) {
|
|
|
|
xfer->stride = 0;
|
|
|
|
xfer->layer_stride = 0;
|
2018-07-12 22:44:55 +01:00
|
|
|
|
2018-11-10 10:25:24 +00:00
|
|
|
map->ptr = ptr + box->x;
|
|
|
|
} else {
|
2018-11-30 06:23:34 +00:00
|
|
|
struct isl_surf *surf = &res->surf;
|
|
|
|
const struct isl_format_layout *fmtl =
|
|
|
|
isl_format_get_layout(surf->format);
|
|
|
|
const unsigned cpp = fmtl->bpb / 8;
|
|
|
|
unsigned x0_el, y0_el;
|
|
|
|
|
2018-11-10 10:25:24 +00:00
|
|
|
get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el);
|
2018-06-24 08:27:58 +01:00
|
|
|
|
2018-11-10 10:25:24 +00:00
|
|
|
xfer->stride = isl_surf_get_row_pitch_B(surf);
|
|
|
|
xfer->layer_stride = isl_surf_get_array_pitch(surf);
|
|
|
|
|
|
|
|
map->ptr = ptr + (y0_el + box->y) * xfer->stride + (x0_el + box->x) * cpp;
|
|
|
|
}
|
2018-06-24 08:27:58 +01:00
|
|
|
}
|
|
|
|
|
2018-01-20 02:57:30 +00:00
|
|
|
static void *
|
|
|
|
iris_transfer_map(struct pipe_context *ctx,
|
|
|
|
struct pipe_resource *resource,
|
|
|
|
unsigned level,
|
|
|
|
enum pipe_transfer_usage usage,
|
|
|
|
const struct pipe_box *box,
|
|
|
|
struct pipe_transfer **ptransfer)
|
|
|
|
{
|
|
|
|
struct iris_context *ice = (struct iris_context *)ctx;
|
|
|
|
struct iris_resource *res = (struct iris_resource *)resource;
|
2018-05-29 01:14:43 +01:00
|
|
|
struct isl_surf *surf = &res->surf;
|
|
|
|
|
2019-01-01 06:03:35 +00:00
|
|
|
/* If we can discard the whole resource, we can also discard the
|
|
|
|
* subrange being accessed.
|
|
|
|
*/
|
|
|
|
if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)
|
|
|
|
usage |= PIPE_TRANSFER_DISCARD_RANGE;
|
|
|
|
|
2018-12-21 11:04:18 +00:00
|
|
|
bool map_would_stall = false;
|
2018-05-29 01:14:43 +01:00
|
|
|
|
2018-12-08 19:40:25 +00:00
|
|
|
if (resource->target != PIPE_BUFFER) {
|
|
|
|
iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res,
|
|
|
|
level, box->z, box->depth,
|
|
|
|
usage & PIPE_TRANSFER_WRITE);
|
|
|
|
}
|
|
|
|
|
2018-11-20 17:00:22 +00:00
|
|
|
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
|
2018-12-21 11:04:18 +00:00
|
|
|
map_would_stall = iris_bo_busy(res->bo);
|
|
|
|
|
|
|
|
for (int i = 0; i < IRIS_BATCH_COUNT; i++)
|
|
|
|
map_would_stall |= iris_batch_references(&ice->batches[i], res->bo);
|
|
|
|
|
|
|
|
if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) &&
|
|
|
|
(usage & PIPE_TRANSFER_MAP_DIRECTLY))
|
|
|
|
return NULL;
|
2018-09-18 23:04:14 +01:00
|
|
|
}
|
|
|
|
|
2018-12-21 11:04:18 +00:00
|
|
|
if (surf->tiling != ISL_TILING_LINEAR &&
|
|
|
|
(usage & PIPE_TRANSFER_MAP_DIRECTLY))
|
2018-06-20 03:22:47 +01:00
|
|
|
return NULL;
|
|
|
|
|
2018-07-06 19:29:51 +01:00
|
|
|
struct iris_transfer *map = slab_alloc(&ice->transfer_pool);
|
2018-05-29 01:14:43 +01:00
|
|
|
struct pipe_transfer *xfer = &map->base;
|
2018-01-20 02:57:30 +00:00
|
|
|
|
2018-05-29 01:14:43 +01:00
|
|
|
if (!map)
|
2018-01-20 02:57:30 +00:00
|
|
|
return NULL;
|
|
|
|
|
2018-07-06 19:29:51 +01:00
|
|
|
memset(map, 0, sizeof(*map));
|
2018-05-29 01:14:43 +01:00
|
|
|
map->dbg = &ice->dbg;
|
|
|
|
|
|
|
|
pipe_resource_reference(&xfer->resource, resource);
|
|
|
|
xfer->level = level;
|
|
|
|
xfer->usage = usage;
|
|
|
|
xfer->box = *box;
|
|
|
|
*ptransfer = xfer;
|
2018-01-20 02:57:30 +00:00
|
|
|
|
2018-12-21 11:04:18 +00:00
|
|
|
/* Avoid using GPU copies for persistent/coherent buffers, as the idea
|
|
|
|
* there is to access them simultaneously on the CPU & GPU. This also
|
|
|
|
* avoids trying to use GPU copies for our u_upload_mgr buffers which
|
|
|
|
* contain state we're constructing for a GPU draw call, which would
|
|
|
|
* kill us with infinite stack recursion.
|
|
|
|
*/
|
|
|
|
bool no_gpu = usage & (PIPE_TRANSFER_PERSISTENT |
|
|
|
|
PIPE_TRANSFER_COHERENT |
|
|
|
|
PIPE_TRANSFER_MAP_DIRECTLY);
|
|
|
|
|
|
|
|
/* GPU copies are not useful for buffer reads. Instead of stalling to
|
|
|
|
* read from the original buffer, we'd simply copy it to a temporary...
|
|
|
|
* then stall (a bit longer) to read from that buffer.
|
|
|
|
*
|
|
|
|
* Images are less clear-cut. Color resolves are destructive, removing
|
|
|
|
* the underlying compression, so we'd rather blit the data to a linear
|
|
|
|
* temporary and map that, to avoid the resolve. (It might be better to
|
|
|
|
* a tiled temporary and use the tiled_memcpy paths...)
|
|
|
|
*/
|
|
|
|
if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) &&
|
|
|
|
res->aux.usage != ISL_AUX_USAGE_CCS_E &&
|
|
|
|
res->aux.usage != ISL_AUX_USAGE_CCS_D) {
|
|
|
|
no_gpu = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (map_would_stall && !no_gpu) {
|
|
|
|
/* If we need a synchronous mapping and the resource is busy,
|
|
|
|
* we copy to/from a linear temporary buffer using the GPU.
|
|
|
|
*/
|
|
|
|
map->batch = &ice->batches[IRIS_BATCH_RENDER];
|
|
|
|
map->blorp = &ice->blorp;
|
|
|
|
iris_map_copy_region(map);
|
2018-05-29 01:14:43 +01:00
|
|
|
} else {
|
2018-12-21 11:04:18 +00:00
|
|
|
/* Otherwise we're free to map on the CPU. Flush if needed. */
|
2019-03-18 07:18:32 +00:00
|
|
|
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
|
|
|
|
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
|
|
|
|
if (iris_batch_references(&ice->batches[i], res->bo))
|
|
|
|
iris_batch_flush(&ice->batches[i]);
|
|
|
|
}
|
2018-12-21 11:04:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (surf->tiling == ISL_TILING_W) {
|
|
|
|
/* TODO: Teach iris_map_tiled_memcpy about W-tiling... */
|
|
|
|
iris_map_s8(map);
|
|
|
|
} else if (surf->tiling != ISL_TILING_LINEAR) {
|
|
|
|
iris_map_tiled_memcpy(map);
|
|
|
|
} else {
|
|
|
|
iris_map_direct(map);
|
|
|
|
}
|
2018-05-29 01:14:43 +01:00
|
|
|
}
|
2018-01-20 02:57:30 +00:00
|
|
|
|
2018-05-29 01:14:43 +01:00
|
|
|
return map->ptr;
|
2018-01-20 02:57:30 +00:00
|
|
|
}
|
|
|
|
|
2018-11-21 09:03:48 +00:00
|
|
|
static void
|
|
|
|
iris_transfer_flush_region(struct pipe_context *ctx,
|
|
|
|
struct pipe_transfer *xfer,
|
|
|
|
const struct pipe_box *box)
|
|
|
|
{
|
|
|
|
struct iris_context *ice = (struct iris_context *)ctx;
|
|
|
|
struct iris_resource *res = (struct iris_resource *) xfer->resource;
|
2019-04-07 07:35:49 +01:00
|
|
|
struct iris_transfer *map = (void *) xfer;
|
|
|
|
|
|
|
|
if (map->staging)
|
|
|
|
iris_flush_staging_region(xfer, box);
|
2018-11-21 09:03:48 +00:00
|
|
|
|
|
|
|
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
|
2019-03-05 09:21:53 +00:00
|
|
|
if (ice->batches[i].contains_draw ||
|
|
|
|
ice->batches[i].cache.render->entries) {
|
2018-11-21 09:03:48 +00:00
|
|
|
iris_batch_maybe_flush(&ice->batches[i], 24);
|
|
|
|
iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-01-20 02:57:30 +00:00
|
|
|
static void
|
2018-07-06 19:29:51 +01:00
|
|
|
iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
|
2018-01-20 02:57:30 +00:00
|
|
|
{
|
2018-07-06 19:29:51 +01:00
|
|
|
struct iris_context *ice = (struct iris_context *)ctx;
|
2018-06-18 05:47:52 +01:00
|
|
|
struct iris_transfer *map = (void *) xfer;
|
2019-04-07 07:35:49 +01:00
|
|
|
|
|
|
|
if (!(xfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT)) {
|
|
|
|
struct pipe_box flush_box = {
|
|
|
|
.x = 0, .y = 0, .z = 0,
|
|
|
|
.width = xfer->box.width,
|
|
|
|
.height = xfer->box.height,
|
|
|
|
.depth = xfer->box.depth,
|
|
|
|
};
|
|
|
|
iris_transfer_flush_region(ctx, xfer, &flush_box);
|
|
|
|
}
|
2018-05-29 01:14:43 +01:00
|
|
|
|
|
|
|
if (map->unmap)
|
|
|
|
map->unmap(map);
|
|
|
|
|
|
|
|
pipe_resource_reference(&xfer->resource, NULL);
|
2018-07-06 19:29:51 +01:00
|
|
|
slab_free(&ice->transfer_pool, map);
|
2018-01-20 02:57:30 +00:00
|
|
|
}
|
|
|
|
|
2018-11-21 08:52:25 +00:00
|
|
|
void
|
|
|
|
iris_flush_and_dirty_for_history(struct iris_context *ice,
|
2018-11-21 09:03:48 +00:00
|
|
|
struct iris_batch *batch,
|
2018-11-21 08:52:25 +00:00
|
|
|
struct iris_resource *res)
|
|
|
|
{
|
|
|
|
if (res->base.target != PIPE_BUFFER)
|
|
|
|
return;
|
|
|
|
|
|
|
|
unsigned flush = PIPE_CONTROL_CS_STALL;
|
2018-12-23 05:24:02 +00:00
|
|
|
|
|
|
|
/* We've likely used the rendering engine (i.e. BLORP) to write to this
|
|
|
|
* surface. Flush the render cache so the data actually lands.
|
|
|
|
*/
|
|
|
|
if (batch->name != IRIS_BATCH_COMPUTE)
|
|
|
|
flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
|
|
|
|
|
2018-11-21 08:52:25 +00:00
|
|
|
uint64_t dirty = 0ull;
|
|
|
|
|
|
|
|
if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
|
|
|
|
flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE |
|
|
|
|
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
dirty |= IRIS_DIRTY_CONSTANTS_VS |
|
|
|
|
IRIS_DIRTY_CONSTANTS_TCS |
|
|
|
|
IRIS_DIRTY_CONSTANTS_TES |
|
|
|
|
IRIS_DIRTY_CONSTANTS_GS |
|
|
|
|
IRIS_DIRTY_CONSTANTS_FS |
|
|
|
|
IRIS_DIRTY_CONSTANTS_CS |
|
|
|
|
IRIS_ALL_DIRTY_BINDINGS;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
|
|
|
|
flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
|
|
|
|
if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
|
|
|
|
flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
|
|
|
|
|
|
|
|
if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
|
|
|
|
flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
|
|
|
|
|
2018-11-21 09:03:48 +00:00
|
|
|
iris_emit_pipe_control_flush(batch, flush);
|
2018-11-21 08:52:25 +00:00
|
|
|
|
|
|
|
ice->state.dirty |= dirty;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:45:05 +00:00
|
|
|
bool
|
|
|
|
iris_resource_set_clear_color(struct iris_context *ice,
|
|
|
|
struct iris_resource *res,
|
|
|
|
union isl_color_value color)
|
|
|
|
{
|
|
|
|
if (memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
|
|
|
|
res->aux.clear_color = color;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
union isl_color_value
|
|
|
|
iris_resource_get_clear_color(const struct iris_resource *res,
|
|
|
|
struct iris_bo **clear_color_bo,
|
|
|
|
uint64_t *clear_color_offset)
|
|
|
|
{
|
|
|
|
assert(res->aux.bo);
|
|
|
|
|
|
|
|
if (clear_color_bo)
|
|
|
|
*clear_color_bo = res->aux.clear_color_bo;
|
|
|
|
if (clear_color_offset)
|
|
|
|
*clear_color_offset = res->aux.clear_color_offset;
|
|
|
|
return res->aux.clear_color;
|
|
|
|
}
|
|
|
|
|
2018-08-08 22:54:09 +01:00
|
|
|
static enum pipe_format
|
|
|
|
iris_resource_get_internal_format(struct pipe_resource *p_res)
|
|
|
|
{
|
|
|
|
struct iris_resource *res = (void *) p_res;
|
|
|
|
return res->internal_format;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct u_transfer_vtbl transfer_vtbl = {
|
|
|
|
.resource_create = iris_resource_create,
|
|
|
|
.resource_destroy = iris_resource_destroy,
|
|
|
|
.transfer_map = iris_transfer_map,
|
|
|
|
.transfer_unmap = iris_transfer_unmap,
|
2018-11-21 09:03:48 +00:00
|
|
|
.transfer_flush_region = iris_transfer_flush_region,
|
2018-08-08 22:54:09 +01:00
|
|
|
.get_internal_format = iris_resource_get_internal_format,
|
|
|
|
.set_stencil = iris_resource_set_separate_stencil,
|
|
|
|
.get_stencil = iris_resource_get_separate_stencil,
|
|
|
|
};
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
void
|
|
|
|
iris_init_screen_resource_functions(struct pipe_screen *pscreen)
|
|
|
|
{
|
2019-03-26 07:25:31 +00:00
|
|
|
pscreen->query_dmabuf_modifiers = iris_query_dmabuf_modifiers;
|
2017-11-24 07:15:14 +00:00
|
|
|
pscreen->resource_create_with_modifiers =
|
|
|
|
iris_resource_create_with_modifiers;
|
2018-08-08 22:54:09 +01:00
|
|
|
pscreen->resource_create = u_transfer_helper_resource_create;
|
2018-07-31 14:47:02 +01:00
|
|
|
pscreen->resource_from_user_memory = iris_resource_from_user_memory;
|
2017-11-24 07:15:14 +00:00
|
|
|
pscreen->resource_from_handle = iris_resource_from_handle;
|
|
|
|
pscreen->resource_get_handle = iris_resource_get_handle;
|
2018-08-08 22:54:09 +01:00
|
|
|
pscreen->resource_destroy = u_transfer_helper_resource_destroy;
|
|
|
|
pscreen->transfer_helper =
|
2018-11-08 05:06:49 +00:00
|
|
|
u_transfer_helper_create(&transfer_vtbl, true, true, false, true);
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
2018-01-20 02:57:30 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
iris_init_resource_functions(struct pipe_context *ctx)
|
|
|
|
{
|
|
|
|
ctx->flush_resource = iris_flush_resource;
|
2018-08-08 22:54:09 +01:00
|
|
|
ctx->transfer_map = u_transfer_helper_transfer_map;
|
|
|
|
ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
|
|
|
|
ctx->transfer_unmap = u_transfer_helper_transfer_unmap;
|
2018-06-07 09:25:35 +01:00
|
|
|
ctx->buffer_subdata = u_default_buffer_subdata;
|
|
|
|
ctx->texture_subdata = u_default_texture_subdata;
|
2018-01-20 02:57:30 +00:00
|
|
|
}
|