iris: Flush for history at various moments
When we blit, transfer, or copy_resource to a buffer, we need to flush to ensure any stale data for that buffer is invalidated in the caches. bind_history will inform us which caches need to be flushed. Also, for any push constant buffers, we need to flag those dirty so that we re-emit 3DSTATE_CONSTANT_*, causing the data to be re-pushed.
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c8579e708e
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@ -378,6 +378,9 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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}
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blorp_batch_finish(&blorp_batch);
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iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *)
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info->dst.resource);
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}
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/**
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@ -432,6 +435,8 @@ iris_resource_copy_region(struct pipe_context *ctx,
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}
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blorp_batch_finish(&blorp_batch);
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iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) dst);
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}
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void
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@ -858,24 +858,41 @@ iris_transfer_map(struct pipe_context *ctx,
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return map->ptr;
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}
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static void
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iris_transfer_flush_region(struct pipe_context *ctx,
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struct pipe_transfer *xfer,
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const struct pipe_box *box)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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struct iris_resource *res = (struct iris_resource *) xfer->resource;
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// XXX: don't emit flushes in both engines...? we may also need to flush
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// even if there isn't a draw yet - may still be stale data in caches...
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for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
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if (ice->batches[i].contains_draw) {
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iris_batch_maybe_flush(&ice->batches[i], 24);
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iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
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}
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}
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}
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static void
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iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer)
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{
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struct iris_context *ice = (struct iris_context *)ctx;
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struct iris_transfer *map = (void *) xfer;
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struct iris_resource *res = (struct iris_resource *) xfer->resource;
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struct isl_surf *surf = &res->surf;
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if (map->unmap)
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map->unmap(map);
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/* XXX: big ol' hack! need to re-emit UBOs. want bind_history? */
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if (surf->tiling == ISL_TILING_LINEAR) {
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ice->state.dirty |= IRIS_DIRTY_CONSTANTS_VS | IRIS_DIRTY_BINDINGS_VS
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| IRIS_DIRTY_CONSTANTS_TCS | IRIS_DIRTY_BINDINGS_TCS
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| IRIS_DIRTY_CONSTANTS_TES | IRIS_DIRTY_BINDINGS_TES
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| IRIS_DIRTY_CONSTANTS_GS | IRIS_DIRTY_BINDINGS_GS
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| IRIS_DIRTY_CONSTANTS_FS | IRIS_DIRTY_BINDINGS_FS;
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// XXX: don't emit flushes in both engines...?
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for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
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if (ice->batches[i].contains_draw) {
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iris_batch_maybe_flush(&ice->batches[i], 24);
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iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
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}
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}
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pipe_resource_reference(&xfer->resource, NULL);
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@ -889,6 +906,7 @@ iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource)
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void
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iris_flush_and_dirty_for_history(struct iris_context *ice,
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struct iris_batch *batch,
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struct iris_resource *res)
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{
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if (res->base.target != PIPE_BUFFER)
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@ -918,11 +936,7 @@ iris_flush_and_dirty_for_history(struct iris_context *ice,
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if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
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flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
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// XXX: don't emit flushes in both engines...?
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for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
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if (ice->batches[i].contains_draw)
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iris_emit_pipe_control_flush(&ice->batches[i], flush);
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}
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iris_emit_pipe_control_flush(batch, flush);
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ice->state.dirty |= dirty;
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}
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@ -939,7 +953,7 @@ static const struct u_transfer_vtbl transfer_vtbl = {
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.resource_destroy = iris_resource_destroy,
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.transfer_map = iris_transfer_map,
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.transfer_unmap = iris_transfer_unmap,
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.transfer_flush_region = u_default_transfer_flush_region,
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.transfer_flush_region = iris_transfer_flush_region,
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.get_internal_format = iris_resource_get_internal_format,
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.set_stencil = iris_resource_set_separate_stencil,
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.get_stencil = iris_resource_get_separate_stencil,
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@ -136,6 +136,7 @@ void iris_get_depth_stencil_resources(struct pipe_resource *res,
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void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
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void iris_flush_and_dirty_for_history(struct iris_context *ice,
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struct iris_batch *batch,
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struct iris_resource *res);
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#endif
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