2019-12-03 11:54:30 +00:00
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/*
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* Copyright © 2019 Raspberry Pi
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "v3dv_private.h"
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#include "drm-uapi/drm_fourcc.h"
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#include "util/format/u_format.h"
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#include "util/u_math.h"
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#include "vk_format_info.h"
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/* These are tunable parameters in the HW design, but all the V3D
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* implementations agree.
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*/
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#define VC5_UIFCFG_BANKS 8
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#define VC5_UIFCFG_PAGE_SIZE 4096
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#define VC5_UIFCFG_XOR_VALUE (1 << 4)
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#define VC5_PAGE_CACHE_SIZE (VC5_UIFCFG_PAGE_SIZE * VC5_UIFCFG_BANKS)
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#define VC5_UBLOCK_SIZE 64
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#define VC5_UIFBLOCK_SIZE (4 * VC5_UBLOCK_SIZE)
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#define VC5_UIFBLOCK_ROW_SIZE (4 * VC5_UIFBLOCK_SIZE)
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#define PAGE_UB_ROWS (VC5_UIFCFG_PAGE_SIZE / VC5_UIFBLOCK_ROW_SIZE)
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#define PAGE_UB_ROWS_TIMES_1_5 ((PAGE_UB_ROWS * 3) >> 1)
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#define PAGE_CACHE_UB_ROWS (VC5_PAGE_CACHE_SIZE / VC5_UIFBLOCK_ROW_SIZE)
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#define PAGE_CACHE_MINUS_1_5_UB_ROWS (PAGE_CACHE_UB_ROWS - PAGE_UB_ROWS_TIMES_1_5)
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/**
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* Computes the HW's UIFblock padding for a given height/cpp.
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*
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* The goal of the padding is to keep pages of the same color (bank number) at
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* least half a page away from each other vertically when crossing between
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* columns of UIF blocks.
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*/
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static uint32_t
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v3d_get_ub_pad(uint32_t cpp, uint32_t height)
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{
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uint32_t utile_h = v3d_utile_height(cpp);
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uint32_t uif_block_h = utile_h * 2;
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uint32_t height_ub = height / uif_block_h;
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uint32_t height_offset_in_pc = height_ub % PAGE_CACHE_UB_ROWS;
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/* For the perfectly-aligned-for-UIF-XOR case, don't add any pad. */
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if (height_offset_in_pc == 0)
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return 0;
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/* Try padding up to where we're offset by at least half a page. */
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if (height_offset_in_pc < PAGE_UB_ROWS_TIMES_1_5) {
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/* If we fit entirely in the page cache, don't pad. */
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if (height_ub < PAGE_CACHE_UB_ROWS)
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return 0;
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else
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return PAGE_UB_ROWS_TIMES_1_5 - height_offset_in_pc;
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}
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/* If we're close to being aligned to page cache size, then round up
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* and rely on XOR.
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*/
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if (height_offset_in_pc > PAGE_CACHE_MINUS_1_5_UB_ROWS)
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return PAGE_CACHE_UB_ROWS - height_offset_in_pc;
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/* Otherwise, we're far enough away (top and bottom) to not need any
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* padding.
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*/
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return 0;
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}
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static void
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v3d_setup_slices(struct v3dv_image *image)
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{
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assert(image->cpp > 0);
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uint32_t width = image->extent.width;
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uint32_t height = image->extent.height;
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uint32_t depth = image->extent.depth;
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/* Note that power-of-two padding is based on level 1. These are not
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* equivalent to just util_next_power_of_two(dimension), because at a
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* level 0 dimension of 9, the level 1 power-of-two padded value is 4,
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* not 8.
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*/
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uint32_t pot_width = 2 * util_next_power_of_two(u_minify(width, 1));
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uint32_t pot_height = 2 * util_next_power_of_two(u_minify(height, 1));
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uint32_t pot_depth = 2 * util_next_power_of_two(u_minify(depth, 1));
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uint32_t utile_w = v3d_utile_width(image->cpp);
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uint32_t utile_h = v3d_utile_height(image->cpp);
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uint32_t uif_block_w = utile_w * 2;
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uint32_t uif_block_h = utile_h * 2;
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uint32_t block_width = vk_format_get_blockwidth(image->vk_format);
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uint32_t block_height = vk_format_get_blockheight(image->vk_format);
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bool msaa = image->samples > VK_SAMPLE_COUNT_1_BIT;
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bool uif_top = msaa;
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assert(image->array_size > 0);
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assert(depth > 0);
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assert(image->levels >= 1);
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uint32_t offset = 0;
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for (int32_t i = image->levels - 1; i >= 0; i--) {
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struct v3d_resource_slice *slice = &image->slices[i];
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uint32_t level_width, level_height, level_depth;
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if (i < 2) {
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level_width = u_minify(width, i);
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level_height = u_minify(height, i);
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} else {
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level_width = u_minify(pot_width, i);
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level_height = u_minify(pot_height, i);
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}
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if (i < 1)
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level_depth = u_minify(depth, i);
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else
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level_depth = u_minify(pot_depth, i);
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if (msaa) {
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level_width *= 2;
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level_height *= 2;
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}
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level_width = DIV_ROUND_UP(level_width, block_width);
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level_height = DIV_ROUND_UP(level_height, block_height);
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if (!image->tiled) {
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slice->tiling = VC5_TILING_RASTER;
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if (image->type == VK_IMAGE_TYPE_1D)
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level_width = align(level_width, 64 / image->cpp);
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} else {
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if ((i != 0 || !uif_top) &&
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(level_width <= utile_w || level_height <= utile_h)) {
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slice->tiling = VC5_TILING_LINEARTILE;
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level_width = align(level_width, utile_w);
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level_height = align(level_height, utile_h);
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} else if ((i != 0 || !uif_top) && level_width <= uif_block_w) {
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slice->tiling = VC5_TILING_UBLINEAR_1_COLUMN;
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level_width = align(level_width, uif_block_w);
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level_height = align(level_height, uif_block_h);
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} else if ((i != 0 || !uif_top) && level_width <= 2 * uif_block_w) {
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slice->tiling = VC5_TILING_UBLINEAR_2_COLUMN;
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level_width = align(level_width, 2 * uif_block_w);
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level_height = align(level_height, uif_block_h);
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} else {
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/* We align the width to a 4-block column of UIF blocks, but we
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* only align height to UIF blocks.
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*/
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level_width = align(level_width, 4 * uif_block_w);
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level_height = align(level_height, uif_block_h);
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slice->ub_pad = v3d_get_ub_pad(image->cpp, level_height);
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level_height += slice->ub_pad * uif_block_h;
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/* If the padding set us to to be aligned to the page cache size,
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* then the HW will use the XOR bit on odd columns to get us
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* perfectly misaligned.
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*/
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if ((level_height / uif_block_h) %
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(VC5_PAGE_CACHE_SIZE / VC5_UIFBLOCK_ROW_SIZE) == 0) {
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slice->tiling = VC5_TILING_UIF_XOR;
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} else {
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slice->tiling = VC5_TILING_UIF_NO_XOR;
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}
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}
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}
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slice->offset = offset;
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slice->stride = level_width * image->cpp;
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slice->padded_height = level_height;
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if (slice->tiling == VC5_TILING_UIF_NO_XOR ||
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slice->tiling == VC5_TILING_UIF_XOR) {
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slice->padded_height_of_output_image_in_uif_blocks =
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slice->padded_height / (2 * v3d_utile_height(image->cpp));
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}
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slice->size = level_height * slice->stride;
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uint32_t slice_total_size = slice->size * level_depth;
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/* The HW aligns level 1's base to a page if any of level 1 or
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* below could be UIF XOR. The lower levels then inherit the
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* alignment for as long as necesary, thanks to being power of
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* two aligned.
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*/
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if (i == 1 &&
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level_width > 4 * uif_block_w &&
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level_height > PAGE_CACHE_MINUS_1_5_UB_ROWS * uif_block_h) {
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slice_total_size = align(slice_total_size, VC5_UIFCFG_PAGE_SIZE);
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}
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offset += slice_total_size;
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}
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image->size = offset;
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/* UIF/UBLINEAR levels need to be aligned to UIF-blocks, and LT only
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* needs to be aligned to utile boundaries. Since tiles are laid out
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* from small to big in memory, we need to align the later UIF slices
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* to UIF blocks, if they were preceded by non-UIF-block-aligned LT
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* slices.
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*
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* We additionally align to 4k, which improves UIF XOR performance.
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*/
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image->alignment = 4096;
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uint32_t page_align_offset =
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align(image->slices[0].offset, image->alignment) - image->slices[0].offset;
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if (page_align_offset) {
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image->size += page_align_offset;
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for (int i = 0; i < image->levels; i++)
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image->slices[i].offset += page_align_offset;
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}
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/* Arrays and cube textures have a stride which is the distance from
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* one full mipmap tree to the next (64b aligned). For 3D textures,
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* we need to program the stride between slices of miplevel 0.
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*/
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if (image->type != VK_IMAGE_TYPE_3D) {
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image->cube_map_stride =
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align(image->slices[0].offset + image->slices[0].size, 64);
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image->size += image->cube_map_stride * (image->array_size - 1);
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} else {
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image->cube_map_stride = image->slices[0].size;
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}
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}
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2019-12-17 07:48:10 +00:00
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uint32_t
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v3dv_layer_offset(const struct v3dv_image *image, uint32_t level, uint32_t layer)
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2019-12-05 11:35:02 +00:00
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{
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2019-12-17 07:48:10 +00:00
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const struct v3d_resource_slice *slice = &image->slices[level];
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2019-12-05 11:35:02 +00:00
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if (image->type == VK_IMAGE_TYPE_3D)
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return slice->offset + layer * slice->size;
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else
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return slice->offset + layer * image->cube_map_stride;
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}
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2019-12-03 11:54:30 +00:00
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VkResult
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v3dv_CreateImage(VkDevice _device,
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const VkImageCreateInfo *pCreateInfo,
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const VkAllocationCallbacks *pAllocator,
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VkImage *pImage)
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{
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V3DV_FROM_HANDLE(v3dv_device, device, _device);
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struct v3dv_image *image = NULL;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
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v3dv_assert(pCreateInfo->mipLevels > 0);
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v3dv_assert(pCreateInfo->arrayLayers > 0);
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v3dv_assert(pCreateInfo->samples > 0);
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v3dv_assert(pCreateInfo->extent.width > 0);
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v3dv_assert(pCreateInfo->extent.height > 0);
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v3dv_assert(pCreateInfo->extent.depth > 0);
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const struct v3dv_format *format = v3dv_get_format(pCreateInfo->format);
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v3dv_assert(format != NULL && format->supported);
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image = vk_zalloc2(&device->alloc, pAllocator, sizeof(*image), 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (!image)
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return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
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image->type = pCreateInfo->imageType;
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image->extent = pCreateInfo->extent;
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image->vk_format = pCreateInfo->format;
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image->format = format;
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image->aspects = vk_format_aspects(image->vk_format);
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image->levels = pCreateInfo->mipLevels;
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image->array_size = pCreateInfo->arrayLayers;
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image->samples = pCreateInfo->samples;
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image->usage = pCreateInfo->usage;
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image->create_flags = pCreateInfo->flags;
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image->tiling = pCreateInfo->tiling;
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image->drm_format_mod = DRM_FORMAT_MOD_INVALID;
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image->tiled = true;
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/* 1D and 1D_ARRAY textures are always raster-order */
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if (image->type == VK_IMAGE_TYPE_1D)
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image->tiled = false;
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image->cpp = vk_format_get_blocksize(image->vk_format);
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v3d_setup_slices(image);
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*pImage = v3dv_image_to_handle(image);
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return VK_SUCCESS;
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}
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2019-12-05 11:35:02 +00:00
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2019-12-16 08:09:40 +00:00
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void
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2019-12-17 07:47:08 +00:00
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v3dv_DestroyImage(VkDevice _device,
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VkImage _image,
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2019-12-16 08:09:40 +00:00
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const VkAllocationCallbacks* pAllocator)
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{
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2019-12-17 07:47:08 +00:00
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V3DV_FROM_HANDLE(v3dv_device, device, _device);
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V3DV_FROM_HANDLE(v3dv_image, image, _image);
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vk_free2(&device->alloc, pAllocator, image);
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2019-12-16 08:09:40 +00:00
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}
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2019-12-05 11:35:02 +00:00
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VkResult
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v3dv_CreateImageView(VkDevice _device,
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const VkImageViewCreateInfo *pCreateInfo,
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const VkAllocationCallbacks *pAllocator,
|
|
|
|
VkImageView *pView)
|
|
|
|
{
|
|
|
|
V3DV_FROM_HANDLE(v3dv_device, device, _device);
|
|
|
|
V3DV_FROM_HANDLE(v3dv_image, image, pCreateInfo->image);
|
|
|
|
struct v3dv_image_view *iview;
|
|
|
|
|
|
|
|
iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
|
|
|
|
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
|
|
|
|
if (iview == NULL)
|
|
|
|
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
|
|
|
|
|
|
|
|
const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
|
|
|
|
|
|
|
|
assert(range->layerCount > 0);
|
|
|
|
assert(range->baseMipLevel < image->levels);
|
|
|
|
|
|
|
|
/* FIXME: we don't handle depth/stencil yet */
|
|
|
|
assert((range->aspectMask &
|
|
|
|
(VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) == 0);
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
switch (image->type) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
assert(range->baseArrayLayer + v3dv_layer_count(image, range) - 1 <=
|
|
|
|
image->array_size);
|
|
|
|
break;
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
assert(range->baseArrayLayer + v3dv_layer_count(image, range) - 1
|
|
|
|
<= u_minify(image->extent.depth, range->baseMipLevel));
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("bad VkImageType");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
iview->image = image;
|
|
|
|
iview->aspects = range->aspectMask;
|
2019-12-16 13:21:29 +00:00
|
|
|
|
|
|
|
iview->base_level = range->baseMipLevel;
|
2019-12-05 11:35:02 +00:00
|
|
|
iview->extent = (VkExtent3D) {
|
2019-12-16 13:21:29 +00:00
|
|
|
.width = u_minify(image->extent.width , iview->base_level),
|
|
|
|
.height = u_minify(image->extent.height, iview->base_level),
|
|
|
|
.depth = u_minify(image->extent.depth , iview->base_level),
|
2019-12-05 11:35:02 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
iview->first_layer = range->baseArrayLayer;
|
|
|
|
iview->last_layer = range->baseArrayLayer +
|
|
|
|
v3dv_layer_count(image, range) - 1;
|
2019-12-17 07:48:10 +00:00
|
|
|
iview->offset =
|
|
|
|
v3dv_layer_offset(image, iview->base_level, iview->first_layer);
|
2019-12-05 11:35:02 +00:00
|
|
|
|
|
|
|
iview->tiling = image->slices[0].tiling;
|
|
|
|
|
|
|
|
iview->vk_format = pCreateInfo->format;
|
|
|
|
iview->format = v3dv_get_format(pCreateInfo->format);
|
|
|
|
assert(iview->format && iview->format->supported);
|
|
|
|
|
|
|
|
const struct util_format_description *desc =
|
|
|
|
vk_format_description(iview->vk_format);
|
|
|
|
iview->swap_rb = desc->swizzle[0] == PIPE_SWIZZLE_Z &&
|
|
|
|
iview->vk_format != VK_FORMAT_B5G6R5_UNORM_PACK16;
|
|
|
|
|
|
|
|
v3dv_get_internal_type_bpp_for_output_format(iview->format->rt_type,
|
|
|
|
&iview->internal_type,
|
|
|
|
&iview->internal_bpp);
|
|
|
|
|
|
|
|
*pView = v3dv_image_view_to_handle(iview);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
2019-12-16 08:09:40 +00:00
|
|
|
|
|
|
|
void
|
2019-12-17 07:47:08 +00:00
|
|
|
v3dv_DestroyImageView(VkDevice _device,
|
2019-12-16 08:09:40 +00:00
|
|
|
VkImageView imageView,
|
|
|
|
const VkAllocationCallbacks* pAllocator)
|
|
|
|
{
|
2019-12-17 07:47:08 +00:00
|
|
|
V3DV_FROM_HANDLE(v3dv_device, device, _device);
|
|
|
|
V3DV_FROM_HANDLE(v3dv_image_view, image_view, imageView);
|
|
|
|
|
|
|
|
vk_free2(&device->alloc, pAllocator, image_view);
|
2019-12-16 08:09:40 +00:00
|
|
|
}
|