2015-04-16 21:43:23 +01:00
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/*
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* Copyright © 2009 Corbin Simpson
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* Copyright © 2015 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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#ifndef AMDGPU_WINSYS_H
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#define AMDGPU_WINSYS_H
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2015-12-06 19:57:05 +00:00
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#include "pipebuffer/pb_cache.h"
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2016-09-07 09:50:59 +01:00
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#include "pipebuffer/pb_slab.h"
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2015-04-16 21:43:23 +01:00
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#include "gallium/drivers/radeon/radeon_winsys.h"
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2018-11-19 17:53:09 +00:00
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#include "addrlib/inc/addrinterface.h"
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2017-10-16 01:59:32 +01:00
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#include "util/simple_mtx.h"
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2016-06-11 12:10:49 +01:00
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#include "util/u_queue.h"
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2015-04-16 21:43:23 +01:00
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#include <amdgpu.h>
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struct amdgpu_cs;
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2018-11-21 07:15:11 +00:00
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#define NUM_SLAB_ALLOCATORS 3
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2016-09-07 09:50:59 +01:00
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2015-04-16 21:43:23 +01:00
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struct amdgpu_winsys {
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struct pipe_reference reference;
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2019-12-23 17:51:57 +00:00
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/* File descriptor which was passed to amdgpu_device_initialize */
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int fd;
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2015-12-06 19:57:05 +00:00
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struct pb_cache bo_cache;
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2018-11-21 07:10:14 +00:00
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/* Each slab buffer can only contain suballocations of equal sizes, so we
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* need to layer the allocators, so that we don't waste too much memory.
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*/
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struct pb_slabs bo_slabs[NUM_SLAB_ALLOCATORS];
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2015-04-16 21:43:23 +01:00
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amdgpu_device_handle dev;
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2017-10-16 01:59:32 +01:00
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simple_mtx_t bo_fence_lock;
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2015-04-16 21:43:23 +01:00
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int num_cs; /* The number of command streams created. */
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2017-01-19 19:32:28 +00:00
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unsigned num_total_rejected_cs;
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2017-07-29 00:14:09 +01:00
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uint32_t surf_index_color;
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uint32_t surf_index_fmask;
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2015-04-16 21:43:23 +01:00
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uint32_t next_bo_unique_id;
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uint64_t allocated_vram;
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uint64_t allocated_gtt;
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2016-08-05 00:28:17 +01:00
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uint64_t mapped_vram;
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uint64_t mapped_gtt;
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2015-04-16 21:43:23 +01:00
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uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
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2016-12-27 16:54:18 +00:00
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uint64_t num_gfx_IBs;
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2016-12-27 17:35:32 +00:00
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uint64_t num_sdma_IBs;
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2017-01-23 20:44:45 +00:00
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uint64_t num_mapped_buffers;
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2017-06-29 18:20:06 +01:00
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uint64_t gfx_bo_list_counter;
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2017-10-07 23:35:59 +01:00
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uint64_t gfx_ib_size_counter;
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2015-04-16 21:43:23 +01:00
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struct radeon_info info;
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2016-03-08 00:19:31 +00:00
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/* multithreaded IB submission */
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2016-06-11 12:10:49 +01:00
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struct util_queue cs_queue;
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2016-03-08 00:19:31 +00:00
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2015-04-16 21:43:23 +01:00
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struct amdgpu_gpu_info amdinfo;
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2015-04-16 18:41:33 +01:00
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ADDR_HANDLE addrlib;
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2016-01-14 18:31:18 +00:00
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2016-06-22 10:22:33 +01:00
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bool check_vm;
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2017-08-29 15:24:45 +01:00
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bool debug_all_bos;
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2017-11-02 14:50:39 +00:00
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bool reserve_vmid;
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2018-06-20 20:17:39 +01:00
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bool zero_all_vram_allocs;
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2019-12-06 09:28:10 +00:00
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bool secure;
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2016-06-22 10:22:33 +01:00
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2016-01-14 18:31:18 +00:00
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/* List of all allocated buffers */
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2017-10-16 01:59:32 +01:00
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simple_mtx_t global_bo_list_lock;
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2016-01-14 18:31:18 +00:00
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struct list_head global_bo_list;
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unsigned num_buffers;
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2018-07-16 18:11:29 +01:00
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2019-09-30 17:36:06 +01:00
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/* Single-linked list of all structs amdgpu_screen_winsys referencing this
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* struct amdgpu_winsys
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*/
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simple_mtx_t sws_list_lock;
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struct amdgpu_screen_winsys *sws_list;
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2018-07-16 18:11:29 +01:00
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/* For returning the same amdgpu_winsys_bo instance for exported
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* and re-imported buffers. */
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2020-02-05 19:47:36 +00:00
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struct hash_table *bo_export_table;
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2018-07-16 18:11:29 +01:00
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simple_mtx_t bo_export_table_lock;
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2015-04-16 21:43:23 +01:00
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};
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2019-06-28 15:06:23 +01:00
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struct amdgpu_screen_winsys {
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struct radeon_winsys base;
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struct amdgpu_winsys *aws;
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int fd;
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2020-01-28 10:07:15 +00:00
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struct pipe_reference reference;
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2019-09-30 17:36:06 +01:00
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struct amdgpu_screen_winsys *next;
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2019-09-30 17:00:50 +01:00
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/* Maps a BO to its KMS handle valid for this DRM file descriptor
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* Protected by amdgpu_winsys::sws_list_lock
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*/
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struct hash_table *kms_handles;
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2019-06-28 15:06:23 +01:00
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};
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static inline struct amdgpu_screen_winsys *
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amdgpu_screen_winsys(struct radeon_winsys *base)
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{
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return (struct amdgpu_screen_winsys*)base;
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}
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2015-04-16 21:43:23 +01:00
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static inline struct amdgpu_winsys *
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amdgpu_winsys(struct radeon_winsys *base)
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{
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2019-06-28 15:06:23 +01:00
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return amdgpu_screen_winsys(base)->aws;
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2015-04-16 21:43:23 +01:00
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}
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2019-06-28 15:06:23 +01:00
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void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *ws);
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2015-04-16 18:41:33 +01:00
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2015-04-16 21:43:23 +01:00
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#endif
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