2020-01-15 00:13:42 +00:00
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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2020-03-27 18:32:38 +00:00
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#include "si_shader_internal.h"
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2020-01-15 00:13:42 +00:00
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#include "sid.h"
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2022-05-24 08:09:00 +01:00
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LLVMValueRef si_get_rel_patch_id(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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{
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2020-08-15 04:56:05 +01:00
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switch (ctx->stage) {
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case MESA_SHADER_TESS_CTRL:
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2020-03-27 18:32:38 +00:00
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return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8);
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2020-01-15 00:13:42 +00:00
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2020-08-15 04:56:05 +01:00
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case MESA_SHADER_TESS_EVAL:
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2020-12-08 23:51:57 +00:00
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return ac_get_arg(&ctx->ac, ctx->args.tes_rel_patch_id);
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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default:
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assert(0);
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return NULL;
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}
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2020-01-15 00:13:42 +00:00
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}
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/* Tessellation shaders pass outputs to the next shader using LDS.
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*
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* LS outputs = TCS inputs
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* TCS outputs = TES inputs
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*
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* The LDS layout is:
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* - TCS inputs for patch 0
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* - TCS inputs for patch 1
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2022-07-13 04:19:52 +01:00
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* - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
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2020-01-15 00:13:42 +00:00
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* - ...
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* - TCS outputs for patch 0 = get_tcs_out_patch0_offset
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* - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
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* - TCS outputs for patch 1
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* - Per-patch TCS outputs for patch 1
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* - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
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* - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
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* - ...
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*
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* All three shaders VS(LS), TCS, TES share the same LDS space.
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*/
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static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
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{
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2020-08-15 04:56:05 +01:00
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assert(ctx->stage == MESA_SHADER_TESS_CTRL);
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2020-01-15 00:13:42 +00:00
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2022-01-04 18:34:16 +00:00
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return util_last_bit64(ctx->shader->selector->info.outputs_written) * 4;
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2020-01-15 00:13:42 +00:00
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}
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static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
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{
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2020-03-27 18:32:38 +00:00
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const struct si_shader_info *info = &ctx->shader->selector->info;
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2020-09-01 22:53:10 +01:00
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unsigned tcs_out_vertices = info->base.tess.tcs_vertices_out;
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2020-03-27 18:32:38 +00:00
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unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
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2022-01-04 18:34:16 +00:00
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unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->info.patch_outputs_written);
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2020-03-27 18:32:38 +00:00
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unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride + num_patch_outputs * 4;
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return LLVMConstInt(ctx->ac.i32, patch_dw_stride, 0);
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2020-01-15 00:13:42 +00:00
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}
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2020-03-27 18:32:38 +00:00
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static LLVMValueRef get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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return LLVMBuildMul(ctx->ac.builder, si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 16, 16),
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LLVMConstInt(ctx->ac.i32, 4, 0), "");
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2020-01-15 00:13:42 +00:00
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}
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2020-03-27 18:32:38 +00:00
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static LLVMValueRef get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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LLVMValueRef patch0_patch_data_offset = get_tcs_out_patch0_patch_data_offset(ctx);
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LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
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2022-05-24 08:09:00 +01:00
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LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx);
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
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2020-01-15 00:13:42 +00:00
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}
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2022-05-06 03:16:27 +01:00
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LLVMValueRef si_get_num_tcs_out_vertices(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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unsigned tcs_out_vertices =
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2020-09-01 22:53:10 +01:00
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ctx->shader->selector ? ctx->shader->selector->info.base.tess.tcs_vertices_out
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2020-03-27 18:32:38 +00:00
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: 0;
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2020-01-15 00:13:42 +00:00
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2022-05-20 10:27:27 +01:00
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/* If !tcs_out_vertices, it's the TCS epilog. */
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2020-08-15 04:56:05 +01:00
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if (ctx->stage == MESA_SHADER_TESS_CTRL && tcs_out_vertices)
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2020-03-27 18:32:38 +00:00
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return LLVMConstInt(ctx->ac.i32, tcs_out_vertices, 0);
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2020-01-15 00:13:42 +00:00
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2020-11-13 03:07:56 +00:00
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return LLVMBuildAdd(ctx->ac.builder,
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si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 5), ctx->ac.i32_1, "");
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2020-01-15 00:13:42 +00:00
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}
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2022-05-07 10:54:02 +01:00
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LLVMValueRef si_get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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unsigned stride;
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2020-08-15 04:56:05 +01:00
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switch (ctx->stage) {
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case MESA_SHADER_VERTEX:
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2022-01-04 18:34:16 +00:00
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stride = ctx->shader->selector->info.lshs_vertex_stride / 4;
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2020-03-27 18:32:38 +00:00
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return LLVMConstInt(ctx->ac.i32, stride, 0);
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2020-08-15 04:56:05 +01:00
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case MESA_SHADER_TESS_CTRL:
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2022-05-12 07:50:17 +01:00
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if (ctx->screen->info.gfx_level >= GFX9 && ctx->shader->is_monolithic) {
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2022-01-04 18:34:16 +00:00
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stride = ctx->shader->key.ge.part.tcs.ls->info.lshs_vertex_stride / 4;
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2020-03-27 18:32:38 +00:00
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return LLVMConstInt(ctx->ac.i32, stride, 0);
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}
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2022-06-09 14:41:52 +01:00
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return GET_FIELD(ctx, VS_STATE_LS_OUT_VERTEX_SIZE);
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2020-03-27 18:32:38 +00:00
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default:
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assert(0);
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return NULL;
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}
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2020-01-15 00:13:42 +00:00
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}
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/* The offchip buffer layout for TCS->TES is
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*
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* - attribute 0 of patch 0 vertex 0
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* - attribute 0 of patch 0 vertex 1
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* - attribute 0 of patch 0 vertex 2
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* ...
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* - attribute 0 of patch 1 vertex 0
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* - attribute 0 of patch 1 vertex 1
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* ...
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* - attribute 1 of patch 0 vertex 0
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* - attribute 1 of patch 0 vertex 1
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* ...
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* - per patch attribute 0 of patch 0
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* - per patch attribute 0 of patch 1
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* ...
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*
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* Note that every attribute has 4 components.
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*/
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static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
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2020-03-27 18:32:38 +00:00
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LLVMValueRef rel_patch_id, LLVMValueRef vertex_index,
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2020-01-15 00:13:42 +00:00
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LLVMValueRef param_index)
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{
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2020-03-27 18:32:38 +00:00
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LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
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LLVMValueRef param_stride, constant16;
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2022-05-06 03:16:27 +01:00
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vertices_per_patch = si_get_num_tcs_out_vertices(ctx);
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2020-03-27 18:32:38 +00:00
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num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6);
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2020-11-13 03:07:56 +00:00
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num_patches = LLVMBuildAdd(ctx->ac.builder, num_patches, ctx->ac.i32_1, "");
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2020-03-27 18:32:38 +00:00
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total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch, num_patches, "");
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constant16 = LLVMConstInt(ctx->ac.i32, 16, 0);
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if (vertex_index) {
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base_addr = ac_build_imad(&ctx->ac, rel_patch_id, vertices_per_patch, vertex_index);
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param_stride = total_vertices;
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} else {
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base_addr = rel_patch_id;
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param_stride = num_patches;
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}
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base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
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base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
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if (!vertex_index) {
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2020-11-13 03:07:56 +00:00
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LLVMValueRef patch_data_offset = si_unpack_param(ctx, ctx->tcs_offchip_layout, 11, 21);
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2020-03-27 18:32:38 +00:00
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base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr, patch_data_offset, "");
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}
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return base_addr;
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2020-01-15 00:13:42 +00:00
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}
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/**
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* Load from LSHS LDS storage.
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*
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2022-07-13 04:19:52 +01:00
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* \param type output value type
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* \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
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* \param dw_addr address in dwords
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2020-01-15 00:13:42 +00:00
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*/
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2020-03-27 18:32:38 +00:00
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static LLVMValueRef lshs_lds_load(struct si_shader_context *ctx, LLVMTypeRef type, unsigned swizzle,
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LLVMValueRef dw_addr)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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LLVMValueRef value;
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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if (swizzle == ~0) {
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LLVMValueRef values[4];
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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for (unsigned chan = 0; chan < 4; chan++)
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values[chan] = lshs_lds_load(ctx, type, chan, dw_addr);
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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return ac_build_gather_values(&ctx->ac, values, 4);
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}
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2020-01-15 00:13:42 +00:00
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2020-03-27 18:32:38 +00:00
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dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, LLVMConstInt(ctx->ac.i32, swizzle, 0), "");
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value = ac_lds_load(&ctx->ac, dw_addr);
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return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
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2020-01-15 00:13:42 +00:00
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}
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2020-03-27 18:32:38 +00:00
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enum si_tess_ring
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{
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TCS_FACTOR_RING,
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TESS_OFFCHIP_RING_TCS,
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TESS_OFFCHIP_RING_TES,
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2020-01-15 00:13:42 +00:00
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};
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2020-03-27 18:32:38 +00:00
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static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx, enum si_tess_ring ring)
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2020-01-15 00:13:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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LLVMBuilderRef builder = ctx->ac.builder;
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LLVMValueRef addr = ac_get_arg(
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&ctx->ac, ring == TESS_OFFCHIP_RING_TES ? ctx->tes_offchip_addr : ctx->tcs_out_lds_layout);
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/* TCS only receives high 13 bits of the address. */
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if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
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addr = LLVMBuildAnd(builder, addr, LLVMConstInt(ctx->ac.i32, 0xfff80000, 0), "");
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}
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if (ring == TCS_FACTOR_RING) {
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2022-05-10 02:47:33 +01:00
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unsigned tf_offset = ctx->screen->hs.tess_offchip_ring_size;
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2020-03-27 18:32:38 +00:00
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addr = LLVMBuildAdd(builder, addr, LLVMConstInt(ctx->ac.i32, tf_offset, 0), "");
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}
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uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
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2022-05-12 07:50:17 +01:00
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if (ctx->screen->info.gfx_level >= GFX11)
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2021-12-18 14:07:48 +00:00
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rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX11_FORMAT_32_FLOAT) |
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S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW);
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2022-05-12 07:50:17 +01:00
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else if (ctx->screen->info.gfx_level >= GFX10)
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2021-03-28 10:11:09 +01:00
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rsrc3 |= S_008F0C_FORMAT(V_008F0C_GFX10_FORMAT_32_FLOAT) |
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2020-03-27 18:32:38 +00:00
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S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) | S_008F0C_RESOURCE_LEVEL(1);
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else
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rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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LLVMValueRef desc[4];
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desc[0] = addr;
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desc[1] = LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
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desc[2] = LLVMConstInt(ctx->ac.i32, 0xffffffff, 0);
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desc[3] = LLVMConstInt(ctx->ac.i32, rsrc3, false);
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return ac_build_gather_values(&ctx->ac, desc, 4);
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2020-01-15 00:13:42 +00:00
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}
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2022-05-24 07:40:05 +01:00
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void si_llvm_preload_tess_rings(struct si_shader_context *ctx)
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2020-01-15 00:13:42 +00:00
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|
|
{
|
2022-05-24 07:40:05 +01:00
|
|
|
ctx->tess_offchip_ring = get_tess_ring_descriptor(
|
|
|
|
ctx, ctx->stage == MESA_SHADER_TESS_CTRL ? TESS_OFFCHIP_RING_TCS : TESS_OFFCHIP_RING_TES);
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi, LLVMTypeRef type,
|
|
|
|
LLVMValueRef vertex_index, LLVMValueRef param_index,
|
|
|
|
unsigned driver_location, unsigned component,
|
2022-05-09 14:28:26 +01:00
|
|
|
unsigned num_components, bool load_input)
|
2020-01-15 00:13:42 +00:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
|
|
|
|
struct si_shader_info *info = &ctx->shader->selector->info;
|
2020-11-14 22:24:11 +00:00
|
|
|
|
2022-05-28 10:52:35 +01:00
|
|
|
assert(ctx->shader->key.ge.opt.same_patch_vertices && !param_index);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2022-05-28 10:52:35 +01:00
|
|
|
ubyte semantic = info->input[driver_location].semantic;
|
|
|
|
/* Load the TCS input from a VGPR. */
|
|
|
|
unsigned func_param = ctx->args.tcs_rel_ids.arg_index + 1 +
|
|
|
|
si_shader_io_get_unique_index(semantic, false) * 4;
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2022-05-28 10:52:35 +01:00
|
|
|
LLVMValueRef value[4];
|
|
|
|
for (unsigned i = component; i < component + num_components; i++) {
|
|
|
|
value[i] = LLVMGetParam(ctx->main_fn, func_param + i);
|
|
|
|
value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
|
2022-05-09 14:28:26 +01:00
|
|
|
}
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
2022-05-03 03:43:38 +01:00
|
|
|
static void si_write_tess_factors(struct si_shader_context *ctx, union si_shader_part_key *key,
|
|
|
|
LLVMValueRef rel_patch_id, LLVMValueRef invocation_id,
|
2020-03-27 18:32:38 +00:00
|
|
|
LLVMValueRef tcs_out_current_patch_data_offset,
|
|
|
|
LLVMValueRef invoc0_tf_outer[4], LLVMValueRef invoc0_tf_inner[2])
|
2020-01-15 00:13:42 +00:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
struct si_shader *shader = ctx->shader;
|
|
|
|
unsigned tess_inner_index, tess_outer_index;
|
|
|
|
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
|
|
|
|
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
|
|
|
|
unsigned stride, outer_comps, inner_comps, i, offset;
|
|
|
|
|
|
|
|
/* Add a barrier before loading tess factors from LDS. */
|
2022-05-03 02:53:12 +01:00
|
|
|
if (!shader->key.ge.part.tcs.epilog.invoc0_tess_factors_are_def) {
|
|
|
|
ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM);
|
2022-05-03 03:43:38 +01:00
|
|
|
|
|
|
|
if (!key->tcs_epilog.noop_s_barrier)
|
|
|
|
ac_build_s_barrier(&ctx->ac, ctx->stage);
|
2022-05-03 02:53:12 +01:00
|
|
|
}
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Do this only for invocation 0, because the tess levels are per-patch,
|
|
|
|
* not per-vertex.
|
|
|
|
*
|
|
|
|
* This can't jump, because invocation 0 executes this. It should
|
|
|
|
* at least mask out the loads and stores for other invocations.
|
|
|
|
*/
|
|
|
|
ac_build_ifcc(&ctx->ac,
|
|
|
|
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, invocation_id, ctx->ac.i32_0, ""), 6503);
|
|
|
|
|
|
|
|
/* Determine the layout of one tess factor element in the buffer. */
|
2021-09-14 04:09:22 +01:00
|
|
|
switch (shader->key.ge.part.tcs.epilog.prim_mode) {
|
2022-01-19 01:43:15 +00:00
|
|
|
case TESS_PRIMITIVE_ISOLINES:
|
2020-03-27 18:32:38 +00:00
|
|
|
stride = 2; /* 2 dwords, 1 vec2 store */
|
|
|
|
outer_comps = 2;
|
|
|
|
inner_comps = 0;
|
|
|
|
break;
|
2022-01-19 01:43:15 +00:00
|
|
|
case TESS_PRIMITIVE_TRIANGLES:
|
2020-03-27 18:32:38 +00:00
|
|
|
stride = 4; /* 4 dwords, 1 vec4 store */
|
|
|
|
outer_comps = 3;
|
|
|
|
inner_comps = 1;
|
|
|
|
break;
|
2022-01-19 01:43:15 +00:00
|
|
|
case TESS_PRIMITIVE_QUADS:
|
2020-03-27 18:32:38 +00:00
|
|
|
stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
|
|
|
|
outer_comps = 4;
|
|
|
|
inner_comps = 2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
inner[i] = LLVMGetUndef(ctx->ac.i32);
|
|
|
|
outer[i] = LLVMGetUndef(ctx->ac.i32);
|
|
|
|
}
|
|
|
|
|
2021-09-14 04:09:22 +01:00
|
|
|
if (shader->key.ge.part.tcs.epilog.invoc0_tess_factors_are_def) {
|
2020-03-27 18:32:38 +00:00
|
|
|
/* Tess factors are in VGPRs. */
|
|
|
|
for (i = 0; i < outer_comps; i++)
|
|
|
|
outer[i] = out[i] = invoc0_tf_outer[i];
|
|
|
|
for (i = 0; i < inner_comps; i++)
|
|
|
|
inner[i] = out[outer_comps + i] = invoc0_tf_inner[i];
|
|
|
|
} else {
|
|
|
|
/* Load tess_inner and tess_outer from LDS.
|
|
|
|
* Any invocation can write them, so we can't get them from a temporary.
|
|
|
|
*/
|
2020-08-15 08:09:34 +01:00
|
|
|
tess_inner_index = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER);
|
|
|
|
tess_outer_index = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
lds_base = tcs_out_current_patch_data_offset;
|
|
|
|
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
|
|
|
|
LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, 0), "");
|
|
|
|
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
|
|
|
|
LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, 0), "");
|
|
|
|
|
|
|
|
for (i = 0; i < outer_comps; i++) {
|
|
|
|
outer[i] = out[i] = lshs_lds_load(ctx, ctx->ac.i32, i, lds_outer);
|
|
|
|
}
|
|
|
|
for (i = 0; i < inner_comps; i++) {
|
|
|
|
inner[i] = out[outer_comps + i] = lshs_lds_load(ctx, ctx->ac.i32, i, lds_inner);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-01-19 01:43:15 +00:00
|
|
|
if (shader->key.ge.part.tcs.epilog.prim_mode == TESS_PRIMITIVE_ISOLINES) {
|
2020-03-27 18:32:38 +00:00
|
|
|
/* For isolines, the hardware expects tess factors in the
|
|
|
|
* reverse order from what NIR specifies.
|
|
|
|
*/
|
|
|
|
LLVMValueRef tmp = out[0];
|
|
|
|
out[0] = out[1];
|
|
|
|
out[1] = tmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Convert the outputs to vectors for stores. */
|
|
|
|
vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
|
|
|
|
vec1 = NULL;
|
|
|
|
|
|
|
|
if (stride > 4)
|
|
|
|
vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
|
|
|
|
|
|
|
|
/* Get the buffer. */
|
|
|
|
buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
|
|
|
|
|
|
|
|
/* Get the offset. */
|
2020-12-08 23:51:57 +00:00
|
|
|
tf_base = ac_get_arg(&ctx->ac, ctx->args.tcs_factor_offset);
|
2020-03-27 18:32:38 +00:00
|
|
|
byteoffset =
|
|
|
|
LLVMBuildMul(ctx->ac.builder, rel_patch_id, LLVMConstInt(ctx->ac.i32, 4 * stride, 0), "");
|
2020-11-14 05:05:00 +00:00
|
|
|
offset = 0;
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Store the dynamic HS control word. */
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level <= GFX8) {
|
2020-11-14 05:05:00 +00:00
|
|
|
ac_build_ifcc(&ctx->ac,
|
|
|
|
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, rel_patch_id, ctx->ac.i32_0, ""), 6504);
|
2022-01-03 19:04:57 +00:00
|
|
|
ac_build_buffer_store_dword(&ctx->ac, buffer, LLVMConstInt(ctx->ac.i32, 0x80000000, 0),
|
2022-04-15 06:08:16 +01:00
|
|
|
NULL, LLVMConstInt(ctx->ac.i32, offset, 0), tf_base, ac_glc);
|
2020-11-14 05:05:00 +00:00
|
|
|
ac_build_endif(&ctx->ac, 6504);
|
2020-03-27 18:32:38 +00:00
|
|
|
offset += 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Store the tessellation factors. */
|
2022-04-15 06:08:16 +01:00
|
|
|
ac_build_buffer_store_dword(&ctx->ac, buffer, vec0, NULL,
|
|
|
|
LLVMBuildAdd(ctx->ac.builder, byteoffset,
|
|
|
|
LLVMConstInt(ctx->ac.i32, offset, 0), ""),
|
|
|
|
tf_base, ac_glc);
|
2020-03-27 18:32:38 +00:00
|
|
|
offset += 16;
|
|
|
|
if (vec1)
|
2022-04-15 06:08:16 +01:00
|
|
|
ac_build_buffer_store_dword(&ctx->ac, buffer, vec1, NULL,
|
|
|
|
LLVMBuildAdd(ctx->ac.builder, byteoffset,
|
|
|
|
LLVMConstInt(ctx->ac.i32, offset, 0), ""),
|
|
|
|
tf_base, ac_glc);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Store the tess factors into the offchip buffer if TES reads them. */
|
2021-09-14 04:09:22 +01:00
|
|
|
if (shader->key.ge.part.tcs.epilog.tes_reads_tess_factors) {
|
2020-03-27 18:32:38 +00:00
|
|
|
LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
|
|
|
|
LLVMValueRef tf_inner_offset;
|
|
|
|
unsigned param_outer, param_inner;
|
|
|
|
|
|
|
|
buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
|
2020-12-08 23:51:57 +00:00
|
|
|
base = ac_get_arg(&ctx->ac, ctx->args.tess_offchip_offset);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2020-08-15 08:09:34 +01:00
|
|
|
param_outer = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER);
|
2020-03-27 18:32:38 +00:00
|
|
|
tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
|
|
|
|
LLVMConstInt(ctx->ac.i32, param_outer, 0));
|
|
|
|
|
2022-01-03 19:04:57 +00:00
|
|
|
outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_comps);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2022-01-03 19:04:57 +00:00
|
|
|
ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec, NULL, tf_outer_offset,
|
2022-04-15 06:08:16 +01:00
|
|
|
base, ac_glc);
|
2020-03-27 18:32:38 +00:00
|
|
|
if (inner_comps) {
|
2020-08-15 08:09:34 +01:00
|
|
|
param_inner = si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER);
|
2020-03-27 18:32:38 +00:00
|
|
|
tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
|
|
|
|
LLVMConstInt(ctx->ac.i32, param_inner, 0));
|
|
|
|
|
2022-01-03 19:04:57 +00:00
|
|
|
inner_vec = ac_build_gather_values(&ctx->ac, inner, inner_comps);
|
|
|
|
ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec, NULL,
|
2022-04-15 06:08:16 +01:00
|
|
|
tf_inner_offset, base, ac_glc);
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ac_build_endif(&ctx->ac, 6503);
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This only writes the tessellation factor levels. */
|
2022-05-06 02:07:12 +01:00
|
|
|
void si_llvm_tcs_build_end(struct si_shader_context *ctx)
|
2020-01-15 00:13:42 +00:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
LLVMBuilderRef builder = ctx->ac.builder;
|
|
|
|
LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
|
|
|
|
|
2022-05-24 08:09:00 +01:00
|
|
|
rel_patch_id = si_get_rel_patch_id(ctx);
|
2020-03-27 18:32:38 +00:00
|
|
|
invocation_id = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
|
|
|
|
tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
|
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level >= GFX9 && !ctx->shader->is_monolithic) {
|
2020-03-27 18:32:38 +00:00
|
|
|
LLVMBasicBlockRef blocks[2] = {LLVMGetInsertBlock(builder), ctx->merged_wrap_if_entry_block};
|
|
|
|
LLVMValueRef values[2];
|
|
|
|
|
|
|
|
ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
|
|
|
|
|
|
|
|
values[0] = rel_patch_id;
|
|
|
|
values[1] = LLVMGetUndef(ctx->ac.i32);
|
|
|
|
rel_patch_id = ac_build_phi(&ctx->ac, ctx->ac.i32, 2, values, blocks);
|
|
|
|
|
|
|
|
values[0] = tf_lds_offset;
|
|
|
|
values[1] = LLVMGetUndef(ctx->ac.i32);
|
|
|
|
tf_lds_offset = ac_build_phi(&ctx->ac, ctx->ac.i32, 2, values, blocks);
|
|
|
|
|
|
|
|
values[0] = invocation_id;
|
|
|
|
values[1] = ctx->ac.i32_1; /* cause the epilog to skip threads */
|
|
|
|
invocation_id = ac_build_phi(&ctx->ac, ctx->ac.i32, 2, values, blocks);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return epilog parameters from this function. */
|
|
|
|
LLVMValueRef ret = ctx->return_value;
|
|
|
|
unsigned vgpr;
|
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level >= GFX9) {
|
2020-03-27 18:32:38 +00:00
|
|
|
ret =
|
|
|
|
si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout, 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout, 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
|
|
|
|
/* Tess offchip and tess factor offsets are at the beginning. */
|
2020-12-08 23:51:57 +00:00
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tcs_factor_offset, 4);
|
2020-03-27 18:32:38 +00:00
|
|
|
vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
|
|
|
|
} else {
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout, GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout, GFX6_SGPR_TCS_OUT_LAYOUT);
|
|
|
|
/* Tess offchip and tess factor offsets are after user SGPRs. */
|
2020-12-08 23:51:57 +00:00
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, GFX6_TCS_NUM_USER_SGPR);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tcs_factor_offset, GFX6_TCS_NUM_USER_SGPR + 1);
|
2020-03-27 18:32:38 +00:00
|
|
|
vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* VGPRs */
|
|
|
|
rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
|
|
|
|
invocation_id = ac_to_float(&ctx->ac, invocation_id);
|
|
|
|
tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
|
|
|
|
|
|
|
|
/* Leave a hole corresponding to the two input VGPRs. This ensures that
|
|
|
|
* the invocation_id output does not alias the tcs_rel_ids input,
|
|
|
|
* which saves a V_MOV on gfx9.
|
|
|
|
*/
|
|
|
|
vgpr += 2;
|
|
|
|
|
|
|
|
ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
|
|
|
|
ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
|
|
|
|
|
2022-05-28 10:52:35 +01:00
|
|
|
struct si_shader_info *info = &ctx->shader->selector->info;
|
|
|
|
if (info->tessfactors_are_def_in_all_invocs) {
|
2020-03-27 18:32:38 +00:00
|
|
|
vgpr++; /* skip the tess factor LDS offset */
|
2022-05-28 10:52:35 +01:00
|
|
|
|
|
|
|
/* get tess factor driver location */
|
|
|
|
int outer_loc = -1;
|
|
|
|
int inner_loc = -1;
|
|
|
|
for (int i = 0; i < info->num_outputs; i++) {
|
|
|
|
unsigned semantic = info->output_semantic[i];
|
|
|
|
if (semantic == VARYING_SLOT_TESS_LEVEL_OUTER)
|
|
|
|
outer_loc = i;
|
|
|
|
else if (semantic == VARYING_SLOT_TESS_LEVEL_INNER)
|
|
|
|
inner_loc = i;
|
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < 6; i++) {
|
2022-05-28 10:52:35 +01:00
|
|
|
int loc = i < 4 ? outer_loc : inner_loc;
|
|
|
|
LLVMValueRef value = loc < 0 ? LLVMGetUndef(ctx->ac.f32) :
|
2022-07-05 12:44:24 +01:00
|
|
|
LLVMBuildLoad2(builder, ctx->ac.f32, ctx->abi.outputs[loc * 4 + i % 4], "");
|
2020-03-27 18:32:38 +00:00
|
|
|
value = ac_to_float(&ctx->ac, value);
|
|
|
|
ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
|
|
|
|
}
|
|
|
|
ctx->return_value = ret;
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Pass TCS inputs from LS to TCS on GFX9. */
|
|
|
|
static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
|
|
|
|
{
|
2021-01-05 08:23:08 +00:00
|
|
|
if (!ctx->shader->is_monolithic)
|
|
|
|
ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
LLVMValueRef ret = ctx->return_value;
|
|
|
|
|
|
|
|
ret = si_insert_input_ptr(ctx, ret, ctx->other_const_and_shader_buffers, 0);
|
|
|
|
ret = si_insert_input_ptr(ctx, ret, ctx->other_samplers_and_images, 1);
|
2020-12-08 23:51:57 +00:00
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 2);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.merged_wave_info, 3);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.tcs_factor_offset, 4);
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level <= GFX10_3)
|
2021-05-11 05:44:00 +01:00
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->args.scratch_offset, 5);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2021-01-12 04:07:50 +00:00
|
|
|
ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS);
|
2020-03-27 18:32:38 +00:00
|
|
|
ret = si_insert_input_ptr(ctx, ret, ctx->bindless_samplers_and_images,
|
|
|
|
8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
|
|
|
|
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->vs_state_bits, 8 + SI_SGPR_VS_STATE_BITS);
|
|
|
|
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_offchip_layout, 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_offsets, 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
|
|
|
|
ret = si_insert_input_ret(ctx, ret, ctx->tcs_out_lds_layout, 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
|
|
|
|
|
|
|
|
unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
|
|
|
|
ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
|
|
|
|
ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id)),
|
|
|
|
vgpr++, "");
|
|
|
|
ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
|
|
|
|
ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.tcs_rel_ids)),
|
|
|
|
vgpr++, "");
|
|
|
|
ctx->return_value = ret;
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
2022-05-06 02:07:12 +01:00
|
|
|
void si_llvm_ls_build_end(struct si_shader_context *ctx)
|
2020-01-15 00:13:42 +00:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
struct si_shader *shader = ctx->shader;
|
|
|
|
struct si_shader_info *info = &shader->selector->info;
|
2022-05-06 02:07:12 +01:00
|
|
|
LLVMValueRef *addrs = ctx->abi.outputs;
|
2020-11-14 22:24:11 +00:00
|
|
|
unsigned ret_offset = 8 + GFX9_TCS_NUM_USER_SGPR + 2;
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2022-05-09 14:28:26 +01:00
|
|
|
if (shader->key.ge.opt.same_patch_vertices) {
|
|
|
|
for (unsigned i = 0; i < info->num_outputs; i++) {
|
|
|
|
unsigned semantic = info->output_semantic[i];
|
|
|
|
int param = si_shader_io_get_unique_index(semantic, false);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2022-05-09 14:28:26 +01:00
|
|
|
for (unsigned chan = 0; chan < 4; chan++) {
|
|
|
|
if (!(info->output_usagemask[i] & (1 << chan)))
|
|
|
|
continue;
|
2020-11-14 22:24:11 +00:00
|
|
|
|
2022-07-05 12:44:24 +01:00
|
|
|
LLVMValueRef value = LLVMBuildLoad2(ctx->ac.builder, ctx->ac.f32, addrs[4 * i + chan], "");
|
2020-11-14 22:24:11 +00:00
|
|
|
|
|
|
|
ctx->return_value = LLVMBuildInsertValue(ctx->ac.builder, ctx->return_value,
|
|
|
|
value, ret_offset + param * 4 + chan, "");
|
|
|
|
}
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level >= GFX9)
|
2020-03-27 18:32:38 +00:00
|
|
|
si_set_ls_return_value_for_tcs(ctx);
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Compile the TCS epilog function. This writes tesselation factors to memory
|
|
|
|
* based on the output primitive type of the tesselator (determined by TES).
|
|
|
|
*/
|
2020-03-27 18:32:38 +00:00
|
|
|
void si_llvm_build_tcs_epilog(struct si_shader_context *ctx, union si_shader_part_key *key)
|
2020-01-15 00:13:42 +00:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
memset(&ctx->args, 0, sizeof(ctx->args));
|
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
if (ctx->screen->info.gfx_level >= GFX9) {
|
2020-03-27 18:32:38 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
2020-12-08 23:51:57 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset);
|
2020-03-27 18:32:38 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); /* wave info */
|
2020-12-08 23:51:57 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tcs_factor_offset);
|
2020-03-27 18:32:38 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_layout);
|
|
|
|
} else {
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_offchip_layout);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->tcs_out_lds_layout);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
|
2020-12-08 23:51:57 +00:00
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset);
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tcs_factor_offset);
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* VGPR gap */
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, NULL); /* VGPR gap */
|
|
|
|
struct ac_arg rel_patch_id; /* patch index within the wave (REL_PATCH_ID) */
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &rel_patch_id);
|
|
|
|
struct ac_arg invocation_id; /* invocation ID within the patch */
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &invocation_id);
|
|
|
|
struct ac_arg
|
|
|
|
tcs_out_current_patch_data_offset; /* LDS offset where tess factors should be loaded from */
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &tcs_out_current_patch_data_offset);
|
|
|
|
|
|
|
|
struct ac_arg tess_factors[6];
|
|
|
|
for (unsigned i = 0; i < 6; i++)
|
|
|
|
ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &tess_factors[i]);
|
|
|
|
|
|
|
|
/* Create the function. */
|
2022-05-12 07:50:17 +01:00
|
|
|
si_llvm_create_func(ctx, "tcs_epilog", NULL, 0, ctx->screen->info.gfx_level >= GFX7 ? 128 : 0);
|
2020-03-27 18:32:38 +00:00
|
|
|
ac_declare_lds_as_pointer(&ctx->ac);
|
|
|
|
|
|
|
|
LLVMValueRef invoc0_tess_factors[6];
|
|
|
|
for (unsigned i = 0; i < 6; i++)
|
|
|
|
invoc0_tess_factors[i] = ac_get_arg(&ctx->ac, tess_factors[i]);
|
|
|
|
|
2022-05-03 03:43:38 +01:00
|
|
|
si_write_tess_factors(ctx, key, ac_get_arg(&ctx->ac, rel_patch_id),
|
2020-03-27 18:32:38 +00:00
|
|
|
ac_get_arg(&ctx->ac, invocation_id),
|
|
|
|
ac_get_arg(&ctx->ac, tcs_out_current_patch_data_offset),
|
|
|
|
invoc0_tess_factors, invoc0_tess_factors + 4);
|
|
|
|
|
|
|
|
LLVMBuildRetVoid(ctx->ac.builder);
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void si_llvm_init_tcs_callbacks(struct si_shader_context *ctx)
|
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
|
2020-01-15 00:13:42 +00:00
|
|
|
}
|