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radeonsi: rename SI_SGPR_RW_BUFFERS to SI_SGPR_INTERNAL_BINDINGS 

They are just internal buffers and images.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8653>
This commit is contained in:
Marek Olšák 2021-01-11 23:07:50 -05:00 committed by Marge Bot
parent 59a478b843
commit dd9801a918
18 changed files with 77 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/gallium/drivers/radeonsi/gfx10_query.c
View File

@ -128,7 +128,7 @@ success:;
sbuf.buffer = &qbuf->buf->b.b;
sbuf.buffer_offset = qbuf->head;
sbuf.buffer_size = sizeof(struct gfx10_sh_query_buffer_mem);
si_set_rw_shader_buffer(sctx, GFX10_GS_QUERY_BUF, &sbuf);
si_set_internal_shader_buffer(sctx, GFX10_GS_QUERY_BUF, &sbuf);
sctx->current_vs_state |= S_VS_STATE_STREAMOUT_QUERY_ENABLED(1);
si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_query);
@ -184,7 +184,7 @@ static bool gfx10_sh_query_end(struct si_context *sctx, struct si_query *rquery)
sctx->num_active_shader_queries--;
if (sctx->num_active_shader_queries <= 0 || !si_is_atom_dirty(sctx, &sctx->atoms.s.shader_query)) {
si_set_rw_shader_buffer(sctx, GFX10_GS_QUERY_BUF, NULL);
si_set_internal_shader_buffer(sctx, GFX10_GS_QUERY_BUF, NULL);
sctx->current_vs_state &= C_VS_STATE_STREAMOUT_QUERY_ENABLED;
/* If a query_begin is followed by a query_end without a draw

6
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
View File

@ -64,7 +64,7 @@ static LLVMValueRef ngg_get_ordered_id(struct si_shader_context *ctx)
static LLVMValueRef ngg_get_query_buf(struct si_shader_context *ctx)
{
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
return ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
LLVMConstInt(ctx->ac.i32, GFX10_GS_QUERY_BUF, false));
@ -269,7 +269,7 @@ static void build_streamout(struct si_shader_context *ctx, struct ngg_streamout
struct si_shader_info *info = &ctx->shader->selector->info;
struct pipe_stream_output_info *so = &ctx->shader->selector->so;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
LLVMValueRef tid = get_thread_id_in_tg(ctx);
LLVMValueRef tmp, tmp2;
LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
@ -1130,7 +1130,7 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out
if (ctx->stage == MESA_SHADER_TESS_EVAL)
ret = si_insert_input_ret(ctx, ret, ctx->args.tess_offchip_offset, 4);
ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers, 8 + SI_SGPR_RW_BUFFERS);
ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS);
ret = si_insert_input_ptr(ctx, ret, ctx->bindless_samplers_and_images,
8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
ret = si_insert_input_ptr(ctx, ret, ctx->const_and_shader_buffers,

2
src/gallium/drivers/radeonsi/si_compute_prim_discard.c
View File

@ -362,7 +362,7 @@ void si_build_prim_discard_compute_shader(struct si_shader_context *ctx)
unsigned num_vs_params = 0;
unsigned param_vertex_id, param_instance_id;
vs_params[num_vs_params++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs, 0))); /* RW_BUFFERS */
vs_params[num_vs_params++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs, 0))); /* INTERNAL RESOURCES */
vs_params[num_vs_params++] = LLVMGetUndef(LLVMTypeOf(LLVMGetParam(vs, 1))); /* BINDLESS */
vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_const_desc);
vs_params[num_vs_params++] = ac_get_arg(&ctx->ac, param_sampler_desc);

4
src/gallium/drivers/radeonsi/si_debug.c
View File

@ -1089,8 +1089,8 @@ void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
si_dump_gfx_shader(sctx, &sctx->gs_shader, log);
si_dump_gfx_shader(sctx, &sctx->ps_shader, log);
si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_RW_BUFFERS], "", "RW buffers",
4, sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots, si_identity,
si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_INTERNAL], "", "RW buffers",
4, sctx->descriptors[SI_DESCS_INTERNAL].num_active_slots, si_identity,
log);
si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log);
si_dump_gfx_descriptors(sctx, tcs_shader, log);

55
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@ -853,8 +853,8 @@ static void si_images_update_needs_color_decompress_mask(struct si_images *image
void si_update_ps_colorbuf0_slot(struct si_context *sctx)
{
struct si_buffer_resources *buffers = &sctx->rw_buffers;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
struct si_buffer_resources *buffers = &sctx->internal_bindings;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_INTERNAL];
unsigned slot = SI_PS_IMAGE_COLORBUF0;
struct pipe_surface *surf = NULL;
@ -916,7 +916,7 @@ void si_update_ps_colorbuf0_slot(struct si_context *sctx)
buffers->enabled_mask &= ~(1llu << slot);
}
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
sctx->descriptors_dirty |= 1u << SI_DESCS_INTERNAL;
}
/* SAMPLER STATES */
@ -1300,15 +1300,16 @@ void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader
/* RING BUFFERS */
void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input)
void si_set_internal_const_buffer(struct si_context *sctx, uint slot,
const struct pipe_constant_buffer *input)
{
si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, input);
si_set_constant_buffer(sctx, &sctx->internal_bindings, SI_DESCS_INTERNAL, slot, input);
}
void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
const struct pipe_shader_buffer *sbuffer)
void si_set_internal_shader_buffer(struct si_context *sctx, uint slot,
const struct pipe_shader_buffer *sbuffer)
{
si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS, slot, sbuffer, true,
si_set_shader_buffer(sctx, &sctx->internal_bindings, SI_DESCS_INTERNAL, slot, sbuffer, true,
RADEON_PRIO_SHADER_RW_BUFFER);
}
@ -1316,8 +1317,8 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource
unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t offset)
{
struct si_buffer_resources *buffers = &sctx->rw_buffers;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
struct si_buffer_resources *buffers = &sctx->internal_bindings;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_INTERNAL];
/* The stride field in the resource descriptor has 14 bits */
assert(stride < (1 << 14));
@ -1402,7 +1403,7 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource
buffers->enabled_mask &= ~(1llu << slot);
}
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
sctx->descriptors_dirty |= 1u << SI_DESCS_INTERNAL;
}
/* INTERNAL CONST BUFFERS */
@ -1420,7 +1421,7 @@ static void si_set_polygon_stipple(struct pipe_context *ctx, const struct pipe_p
cb.user_buffer = stipple;
cb.buffer_size = sizeof(stipple);
si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
si_set_internal_const_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &cb);
}
/* TEXTURE METADATA ENABLE/DISABLE */
@ -1548,15 +1549,15 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
/* Streamout buffers. (other internal buffers can't be invalidated) */
if (!buffer || buffer->bind_history & PIPE_BIND_STREAM_OUTPUT) {
for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
struct si_buffer_resources *buffers = &sctx->rw_buffers;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
struct si_buffer_resources *buffers = &sctx->internal_bindings;
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_INTERNAL];
struct pipe_resource *buffer = buffers->buffers[i];
if (!buffer || (buf && buffer != buf))
continue;
si_set_buf_desc_address(si_resource(buffer), buffers->offsets[i], descs->list + i * 4);
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
sctx->descriptors_dirty |= 1u << SI_DESCS_INTERNAL;
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer), RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER, true);
@ -1992,8 +1993,8 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;
if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) {
si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
if (sctx->shader_pointers_dirty & (1 << SI_DESCS_INTERNAL)) {
si_emit_global_shader_pointers(sctx, &sctx->descriptors[SI_DESCS_INTERNAL]);
}
radeon_begin(&sctx->gfx_cs);
@ -2008,7 +2009,7 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx)
si_emit_consecutive_shader_pointers(sctx, SI_DESCS_SHADER_MASK(GEOMETRY),
sh_base[PIPE_SHADER_GEOMETRY]);
sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE);
sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_INTERNAL, SI_DESCS_FIRST_COMPUTE);
if (sctx->vertex_buffer_pointer_dirty && sctx->num_vertex_elements) {
/* Find the location of the VB descriptor pointer. */
@ -2550,12 +2551,12 @@ void si_init_all_descriptors(struct si_context *sctx)
memcpy(desc->list + j * 8, null_texture_descriptor, 8 * 4);
}
si_init_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS],
SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
si_init_buffer_resources(&sctx->internal_bindings, &sctx->descriptors[SI_DESCS_INTERNAL],
SI_NUM_INTERNAL_BINDINGS, SI_SGPR_INTERNAL_BINDINGS,
/* The second priority is used by
* const buffers in RW buffer slots. */
RADEON_PRIO_SHADER_RINGS, RADEON_PRIO_CONST_BUFFER);
sctx->descriptors[SI_DESCS_RW_BUFFERS].num_active_slots = SI_NUM_RW_BUFFERS;
sctx->descriptors[SI_DESCS_INTERNAL].num_active_slots = SI_NUM_INTERNAL_BINDINGS;
/* Initialize an array of 1024 bindless descriptors, when the limit is
* reached, just make it larger and re-upload the whole array.
@ -2629,7 +2630,7 @@ bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
bool si_upload_compute_shader_descriptors(struct si_context *sctx)
{
/* Does not update rw_buffers as that is not needed for compute shaders
/* This does not update internal bindings as that is not needed for compute shaders
* and the input buffer is using the same SGPR's anyway.
*/
const unsigned mask =
@ -2647,7 +2648,7 @@ void si_release_all_descriptors(struct si_context *sctx)
si_release_sampler_views(&sctx->samplers[i]);
si_release_image_views(&sctx->images[i]);
}
si_release_buffer_resources(&sctx->rw_buffers, &sctx->descriptors[SI_DESCS_RW_BUFFERS]);
si_release_buffer_resources(&sctx->internal_bindings, &sctx->descriptors[SI_DESCS_INTERNAL]);
for (i = 0; i < SI_NUM_VERTEX_BUFFERS; i++)
pipe_vertex_buffer_unreference(&sctx->vertex_buffer[i]);
@ -2683,7 +2684,7 @@ bool si_gfx_resources_check_encrypted(struct si_context *sctx)
use_encrypted_bo |= si_image_views_check_encrypted(sctx, &sctx->images[i],
u_bit_consecutive(0, current_shader[i]->cso->info.base.num_images));
}
use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
use_encrypted_bo |= si_buffer_resources_check_encrypted(sctx, &sctx->internal_bindings);
struct si_state_blend *blend = sctx->queued.named.blend;
for (int i = 0; i < sctx->framebuffer.state.nr_cbufs && !use_encrypted_bo; i++) {
@ -2739,7 +2740,7 @@ void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx)
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[i]);
si_image_views_begin_new_cs(sctx, &sctx->images[i]);
}
si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
si_buffer_resources_begin_new_cs(sctx, &sctx->internal_bindings);
si_vertex_buffers_begin_new_cs(sctx);
if (sctx->bo_list_add_all_resident_resources)
@ -2761,7 +2762,7 @@ bool si_compute_resources_check_encrypted(struct si_context *sctx)
return si_buffer_resources_check_encrypted(sctx, &sctx->const_and_shader_buffers[sh]) ||
si_sampler_views_check_encrypted(sctx, &sctx->samplers[sh], info->base.textures_used) ||
si_image_views_check_encrypted(sctx, &sctx->images[sh], u_bit_consecutive(0, info->base.num_images)) ||
si_buffer_resources_check_encrypted(sctx, &sctx->rw_buffers);
si_buffer_resources_check_encrypted(sctx, &sctx->internal_bindings);
}
void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
@ -2771,7 +2772,7 @@ void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);
si_image_views_begin_new_cs(sctx, &sctx->images[sh]);
si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
si_buffer_resources_begin_new_cs(sctx, &sctx->internal_bindings);
if (sctx->bo_list_add_all_resident_resources)
si_resident_buffers_add_all_to_bo_list(sctx);

10
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -656,11 +656,11 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
}
}
si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
si_set_internal_const_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
}
uint64_t max_threads_per_block;

2
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -1068,7 +1068,7 @@ struct si_context {
unsigned shader_needs_decompress_mask;
unsigned inlinable_uniforms_valid_mask;
uint32_t inlinable_uniforms[SI_NUM_SHADERS][MAX_INLINABLE_UNIFORMS];
struct si_buffer_resources rw_buffers;
struct si_buffer_resources internal_bindings;
struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
struct si_samplers samplers[SI_NUM_SHADERS];
struct si_images images[SI_NUM_SHADERS];

4
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -252,7 +252,7 @@ static void declare_per_stage_desc_pointers(struct si_shader_context *ctx, bool
static void declare_global_desc_pointers(struct si_shader_context *ctx)
{
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->rw_buffers);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_DESC_PTR, &ctx->internal_bindings);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_CONST_IMAGE_PTR,
&ctx->bindless_samplers_and_images);
}
@ -495,7 +495,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
/* TCS return values are inputs to the TCS epilog.
*
* param_tcs_offchip_offset, param_tcs_factor_offset,
* param_tcs_offchip_layout, and param_rw_buffers
* param_tcs_offchip_layout, and internal_bindings
* should be passed to the epilog.
*/
for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)

2
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -166,7 +166,7 @@ struct si_context;
/* SGPR user data indices */
enum
{
SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
SI_SGPR_INTERNAL_BINDINGS,
SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES,
SI_SGPR_CONST_AND_SHADER_BUFFERS, /* or just a constant buffer 0 pointer */
SI_SGPR_SAMPLERS_AND_IMAGES,

4
src/gallium/drivers/radeonsi/si_shader_internal.h
View File

@ -78,7 +78,7 @@ struct si_shader_context {
struct ac_arg other_const_and_shader_buffers;
struct ac_arg other_samplers_and_images;
struct ac_arg rw_buffers;
struct ac_arg internal_bindings;
struct ac_arg bindless_samplers_and_images;
struct ac_arg small_prim_cull_info;
/* API VS */
@ -224,7 +224,7 @@ LLVMValueRef si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueR
struct ac_arg param, unsigned return_index);
LLVMValueRef si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
struct ac_arg param, unsigned return_index);
LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx);
LLVMValueRef si_prolog_get_internal_bindings(struct si_shader_context *ctx);
void si_llvm_emit_barrier(struct si_shader_context *ctx);
void si_llvm_declare_esgs_ring(struct si_shader_context *ctx);
LLVMValueRef si_unpack_param(struct si_shader_context *ctx, struct ac_arg param, unsigned rshift,

4
src/gallium/drivers/radeonsi/si_shader_llvm.c
View File

@ -305,12 +305,12 @@ LLVMValueRef si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret
return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
}
LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
LLVMValueRef si_prolog_get_internal_bindings(struct si_shader_context *ctx)
{
LLVMValueRef ptr[2], list;
bool merged_shader = si_is_merged_shader(ctx->shader);
ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_INTERNAL_BINDINGS);
list =
LLVMBuildIntToPtr(ctx->ac.builder, ptr[0], ac_array_in_const32_addr_space(ctx->ac.v4i32), "");
return list;

8
src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
View File

@ -128,7 +128,7 @@ static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
ret = si_insert_input_ret(ctx, ret, ctx->args.merged_wave_info, 3);
ret = si_insert_input_ret(ctx, ret, ctx->args.scratch_offset, 5);
ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers, 8 + SI_SGPR_RW_BUFFERS);
ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS);
ret = si_insert_input_ptr(ctx, ret, ctx->bindless_samplers_and_images,
8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
if (ctx->screen->use_ngg) {
@ -331,7 +331,7 @@ void si_preload_esgs_ring(struct si_shader_context *ctx)
if (ctx->screen->info.chip_class <= GFX8) {
unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? SI_GS_RING_ESGS : SI_ES_RING_ESGS;
LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, 0);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
} else {
@ -350,7 +350,7 @@ void si_preload_gs_rings(struct si_shader_context *ctx)
const struct si_shader_selector *sel = ctx->shader->selector;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, SI_RING_GSVS, 0);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
LLVMValueRef base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
/* The conceptual layout of the GSVS ring is
@ -452,7 +452,7 @@ struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen,
si_llvm_create_main_func(&ctx, false);
LLVMValueRef buf_ptr = ac_get_arg(&ctx.ac, ctx.rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx.ac, ctx.internal_bindings);
ctx.gsvs_ring[0] =
ac_build_load_to_sgpr(&ctx.ac, buf_ptr, LLVMConstInt(ctx.ac.i32, SI_RING_GSVS, 0));

12
src/gallium/drivers/radeonsi/si_shader_llvm_ps.c
View File

@ -40,7 +40,7 @@ static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
LLVMValueRef desc = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef desc = ac_get_arg(&ctx->ac, ctx->internal_bindings);
LLVMValueRef buf_index = LLVMConstInt(ctx->ac.i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
@ -69,7 +69,7 @@ static LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi)
/* Load the image descriptor. */
STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
ptr =
LLVMBuildPointerCast(ctx->ac.builder, ptr, ac_array_in_const32_addr_space(ctx->ac.v8i32), "");
image =
@ -576,7 +576,7 @@ static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi, unsigned max_ou
}
static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
LLVMValueRef param_rw_buffers,
LLVMValueRef param_internal_bindings,
struct ac_arg param_pos_fixed_pt)
{
LLVMBuilderRef builder = ctx->ac.builder;
@ -591,7 +591,7 @@ static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
/* Load the buffer descriptor. */
slot = LLVMConstInt(ctx->ac.i32, SI_PS_CONST_POLY_STIPPLE, 0);
desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
desc = ac_build_load_to_sgpr(&ctx->ac, param_internal_bindings, slot);
/* The stipple pattern is 32x32, each row has 32 bits. */
offset = LLVMBuildMul(builder, address[1], LLVMConstInt(ctx->ac.i32, 4, 0), "");
@ -666,7 +666,7 @@ void si_llvm_build_ps_prolog(struct si_shader_context *ctx, union si_shader_part
/* Polygon stippling. */
if (key->ps_prolog.states.poly_stipple) {
LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
LLVMValueRef list = si_prolog_get_internal_bindings(ctx);
si_llvm_emit_polygon_stipple(ctx, list, pos_fixed_pt);
}
@ -876,7 +876,7 @@ void si_llvm_build_ps_epilog(struct si_shader_context *ctx, union si_shader_part
memset(&ctx->args, 0, sizeof(ctx->args));
/* Declare input SGPRs. */
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->rw_buffers);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->internal_bindings);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->bindless_samplers_and_images);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->const_and_shader_buffers);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->samplers_and_images);

4
src/gallium/drivers/radeonsi/si_shader_llvm_tess.c
View File

@ -593,7 +593,7 @@ static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx, unsig
int i, offset;
slot = LLVMConstInt(ctx->ac.i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
buf = ac_get_arg(&ctx->ac, ctx->rw_buffers);
buf = ac_get_arg(&ctx->ac, ctx->internal_bindings);
buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
offset = sysval == SYSTEM_VALUE_TESS_LEVEL_INNER_DEFAULT ? 4 : 0;
@ -934,7 +934,7 @@ static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
ret = si_insert_input_ret(ctx, ret, ctx->args.tcs_factor_offset, 4);
ret = si_insert_input_ret(ctx, ret, ctx->args.scratch_offset, 5);
ret = si_insert_input_ptr(ctx, ret, ctx->rw_buffers, 8 + SI_SGPR_RW_BUFFERS);
ret = si_insert_input_ptr(ctx, ret, ctx->internal_bindings, 8 + SI_SGPR_INTERNAL_BINDINGS);
ret = si_insert_input_ptr(ctx, ret, ctx->bindless_samplers_and_images,
8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);

6
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
View File

@ -328,7 +328,7 @@ void si_llvm_emit_streamout(struct si_shader_context *ctx, struct si_shader_outp
* enabled buffer. */
LLVMValueRef so_write_offset[4] = {};
LLVMValueRef so_buffers[4];
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
for (i = 0; i < 4; i++) {
if (!so->stride[i])
@ -369,7 +369,7 @@ static void si_llvm_emit_clipvertex(struct si_shader_context *ctx, struct ac_exp
unsigned chan;
unsigned const_chan;
LLVMValueRef base_elt;
LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->internal_bindings);
LLVMValueRef constbuf_index = LLVMConstInt(ctx->ac.i32, SI_VS_CONST_CLIP_PLANES, 0);
LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
unsigned clipdist_mask = ctx->shader->selector->clipdist_mask &
@ -1009,7 +1009,7 @@ void si_llvm_build_vs_prolog(struct si_shader_context *ctx, union si_shader_part
LLVMValueRef instance_divisor_constbuf = NULL;
if (key->vs_prolog.states.instance_divisor_is_fetched) {
LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
LLVMValueRef list = si_prolog_get_internal_bindings(ctx);
LLVMValueRef buf_index = LLVMConstInt(ctx->ac.i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
instance_divisor_constbuf = ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
}

8
src/gallium/drivers/radeonsi/si_state.c
View File

@ -717,7 +717,7 @@ static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_s
cb.user_buffer = state->ucp;
cb.buffer_offset = 0;
cb.buffer_size = 4 * 4 * 8;
si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
}
static void si_emit_clip_state(struct si_context *sctx)
@ -2889,7 +2889,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
assert(0);
}
constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
}
@ -4813,7 +4813,7 @@ static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
cb.user_buffer = NULL;
cb.buffer_offset = 0;
cb.buffer_size = 0xffffffff;
si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
}
}
@ -4898,7 +4898,7 @@ static void si_set_tess_state(struct pipe_context *ctx, const float default_oute
cb.buffer_offset = 0;
cb.buffer_size = sizeof(array);
si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
}
static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)

11
src/gallium/drivers/radeonsi/si_state.h
View File

@ -383,7 +383,7 @@ enum
GFX10_GS_QUERY_BUF,
SI_NUM_RW_BUFFERS,
SI_NUM_INTERNAL_BINDINGS,
};
/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
@ -404,7 +404,7 @@ enum
SI_NUM_SHADER_DESCS,
};
#define SI_DESCS_RW_BUFFERS 0
#define SI_DESCS_INTERNAL 0
#define SI_DESCS_FIRST_SHADER 1
#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
@ -520,9 +520,10 @@ void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
void si_emit_graphics_shader_pointers(struct si_context *sctx);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx, uint slot, const struct pipe_constant_buffer *input);
void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
const struct pipe_shader_buffer *sbuffer);
void si_set_internal_const_buffer(struct si_context *sctx, uint slot,
const struct pipe_constant_buffer *input);
void si_set_internal_shader_buffer(struct si_context *sctx, uint slot,
const struct pipe_shader_buffer *sbuffer);
void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
uint64_t new_active_mask);
void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel);

6
src/gallium/drivers/radeonsi/si_state_streamout.c
View File

@ -197,14 +197,14 @@ static void si_set_streamout_targets(struct pipe_context *ctx, unsigned num_targ
sbuf.buffer_size = targets[i]->buffer_offset + targets[i]->buffer_size;
}
si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, &sbuf);
si_set_internal_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, &sbuf);
si_resource(targets[i]->buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT;
} else {
si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
si_set_internal_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
}
}
for (; i < old_num_targets; i++)
si_set_rw_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
si_set_internal_shader_buffer(sctx, SI_VS_STREAMOUT_BUF0 + i, NULL);
if (wait_now)
sctx->emit_cache_flush(sctx, &sctx->gfx_cs);