mesa/src/amd
Bas Nieuwenhuizen 84889a982c radv: Move all the dirty flags from TES binding to TCS binding.
With merged shaders we might not have an explicit TES.

Fixes: 879ddf9720 ("radv: rework binding shaders to cmdbuf by introducing new helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8939
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22784>
(cherry picked from commit df08ed7d1c)
2023-05-03 14:41:58 +01:00
..
addrlib amd: update addrlib 2023-03-29 20:36:09 +00:00
ci radv: do not allow 1D block-compressed images with (extended) storage on GFX6 2023-04-26 17:37:24 +01:00
common ac/nir: fix 8-bit/10-bit PS exports clamping 2023-05-01 09:02:38 +01:00
compiler aco: don't move exec writes around exec writes 2023-05-01 09:02:25 +01:00
drm-shim
llvm ac/llvm: support shifts on 16 bit vec2 2023-04-26 17:37:26 +01:00
registers amd/registers: use gfx9 packet definitions for gfx940 2023-04-06 15:00:54 +00:00
vulkan radv: Move all the dirty flags from TES binding to TCS binding. 2023-05-03 14:41:58 +01:00
.clang-format amd: Add radv_foreach_stage to ForEachMacros. 2023-03-27 08:29:35 +00:00
meson.build