mesa/src/freedreno
Dmitry Baryshkov fc5dd4035a freedreno/a5xx: add SP clock control register
Add GPMU_GPMU_SP_CLOCK_CONTROL register. Duplicated GPGMU is not a typo,
vendor kernel names it A5XX_GPMU_GPMU_SP_CLOCK_CONTROL.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22429>
2023-04-12 08:48:27 +00:00
..
.gitlab-ci freedreno+tu: Big GMEM support 2023-03-18 18:21:53 +00:00
afuc freedreno/afuc: Add raw mode for disasm 2023-03-25 16:21:28 +00:00
ci Uprev Piglit to 355ad6bcb2cb3d9e030b7c6eef2b076b0dfb4d63 2023-04-12 08:04:55 +00:00
common freedreno: Fix or/and'ing two BitmaskEnums 2023-04-01 13:53:31 +00:00
computerator freedreno/computerator: Add support for a7xx 2023-03-30 23:40:48 +00:00
decode freedreno/decode: fix possible overflow 2023-03-23 18:56:34 +00:00
drm freedreno/drm: Disable threaded-submit for msm 2023-03-30 19:42:01 +00:00
drm-shim
ds
fdl
ir2
ir3 nir: Combine if_uses with instruction uses 2023-04-07 23:48:03 +00:00
isa
perfcntrs
registers freedreno/a5xx: add SP clock control register 2023-04-12 08:48:27 +00:00
rnn freedreno/rnn: Fix reg names for regs with variants 2023-03-23 17:54:57 +00:00
vulkan vulkan/pipeline_cache: add cache parameter to deserialize() function 2023-04-10 09:14:30 +00:00
.clang-format
.dir-locals.el
.editorconfig
meson.build ci/freedreno: do not build tools executables without explicitly enabling them 2023-03-23 18:56:34 +00:00