mirror of https://gitlab.freedesktop.org/mesa/mesa
502 lines
15 KiB
C
502 lines
15 KiB
C
/*
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* Copyright © 2022 Imagination Technologies Ltd.
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*
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* Based on radv_radeon_winsys.h which is:
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef PVR_WINSYS_H
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#define PVR_WINSYS_H
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#include <pthread.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <vulkan/vulkan.h>
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#include "hwdef/rogue_hw_defs.h"
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#include "pvr_limits.h"
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#include "pvr_rogue_fw.h"
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#include "pvr_types.h"
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#include "util/macros.h"
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#include "util/vma.h"
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#include "vk_sync.h"
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struct pvr_device_info;
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struct pvr_device_runtime_info;
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struct pvr_winsys_heaps {
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struct pvr_winsys_heap *general_heap;
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struct pvr_winsys_heap *pds_heap;
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struct pvr_winsys_heap *rgn_hdr_heap;
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struct pvr_winsys_heap *transfer_3d_heap;
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struct pvr_winsys_heap *usc_heap;
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struct pvr_winsys_heap *vis_test_heap;
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};
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struct pvr_winsys_static_data_offsets {
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uint64_t eot;
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uint64_t fence;
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uint64_t vdm_sync;
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uint64_t yuv_csc;
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};
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struct pvr_winsys_heap {
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struct pvr_winsys *ws;
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pvr_dev_addr_t base_addr;
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pvr_dev_addr_t reserved_addr;
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uint64_t size;
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uint64_t reserved_size;
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uint32_t page_size;
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uint32_t log2_page_size;
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struct util_vma_heap vma_heap;
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int ref_count;
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pthread_mutex_t lock;
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/* These are the offsets from the base at which static data might be
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* uploaded. Some of these might be invalid since the kernel might not
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* return all of these offsets per each heap as they might not be
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* applicable.
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* You should know which to use beforehand. There should be no need to check
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* whether an offset is valid or invalid.
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*/
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struct pvr_winsys_static_data_offsets static_data_offsets;
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};
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enum pvr_winsys_bo_type {
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PVR_WINSYS_BO_TYPE_GPU = 0,
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PVR_WINSYS_BO_TYPE_DISPLAY = 1,
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};
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/**
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* \brief Flag passed to #pvr_winsys_ops.buffer_create to indicate that the
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* buffer should be CPU accessible. This is required in order to map the buffer
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* using #pvr_winsys_ops.buffer_map.
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*/
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#define PVR_WINSYS_BO_FLAG_CPU_ACCESS BITFIELD_BIT(0U)
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/**
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* \brief Flag passed to #pvr_winsys_ops.buffer_create to indicate that, when
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* the buffer is mapped to the GPU using #pvr_winsys.vma_map, it should be
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* mapped uncached.
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*/
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#define PVR_WINSYS_BO_FLAG_GPU_UNCACHED BITFIELD_BIT(1U)
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/**
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* \brief Flag passed to #pvr_winsys_ops.buffer_create to indicate that, when
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* the buffer is mapped to the GPU using #pvr_winsys.vma_map, it should only be
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* accessible to the Parameter Manager unit and firmware processor.
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*/
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#define PVR_WINSYS_BO_FLAG_PM_FW_PROTECT BITFIELD_BIT(2U)
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/**
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* \brief Flag passed to #pvr_winsys_ops.buffer_create to indicate that the
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* buffer should be zeroed at allocation time.
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*/
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#define PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC BITFIELD_BIT(3U)
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struct pvr_winsys_bo {
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struct pvr_winsys *ws;
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void *map;
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uint64_t size;
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bool is_imported;
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#if defined(HAVE_VALGRIND)
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char *vbits;
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#endif /* defined(HAVE_VALGRIND) */
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};
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struct pvr_winsys_vma {
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struct pvr_winsys_heap *heap;
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/* Buffer and offset this vma is bound to. */
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struct pvr_winsys_bo *bo;
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VkDeviceSize bo_offset;
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pvr_dev_addr_t dev_addr;
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uint64_t size;
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uint64_t mapped_size;
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};
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struct pvr_winsys_free_list {
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struct pvr_winsys *ws;
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};
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struct pvr_winsys_rt_dataset_create_info {
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/* Local freelist */
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struct pvr_winsys_free_list *local_free_list;
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/* ISP register values */
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uint32_t isp_merge_lower_x;
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uint32_t isp_merge_lower_y;
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uint32_t isp_merge_scale_x;
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uint32_t isp_merge_scale_y;
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uint32_t isp_merge_upper_x;
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uint32_t isp_merge_upper_y;
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uint32_t isp_mtile_size;
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/* PPP register values */
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uint64_t ppp_multi_sample_ctl;
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uint64_t ppp_multi_sample_ctl_y_flipped;
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uint32_t ppp_screen;
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/* TE register values */
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uint32_t te_aa;
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uint32_t te_mtile1;
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uint32_t te_mtile2;
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uint32_t te_screen;
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/* Allocations and associated information */
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pvr_dev_addr_t vheap_table_dev_addr;
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pvr_dev_addr_t rtc_dev_addr;
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pvr_dev_addr_t tpc_dev_addr;
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uint32_t tpc_stride;
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uint32_t tpc_size;
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struct {
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pvr_dev_addr_t pm_mlist_dev_addr;
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pvr_dev_addr_t macrotile_array_dev_addr;
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pvr_dev_addr_t rgn_header_dev_addr;
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} rt_datas[ROGUE_NUM_RTDATAS];
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uint64_t rgn_header_size;
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/* Miscellaneous */
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uint32_t mtile_stride;
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uint16_t max_rts;
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};
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struct pvr_winsys_rt_dataset {
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struct pvr_winsys *ws;
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};
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enum pvr_winsys_ctx_priority {
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PVR_WINSYS_CTX_PRIORITY_LOW,
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PVR_WINSYS_CTX_PRIORITY_MEDIUM,
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PVR_WINSYS_CTX_PRIORITY_HIGH,
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};
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struct pvr_winsys_render_ctx_create_info {
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enum pvr_winsys_ctx_priority priority;
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pvr_dev_addr_t vdm_callstack_addr;
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struct pvr_winsys_render_ctx_static_state {
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uint64_t vdm_ctx_state_base_addr;
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uint64_t geom_ctx_state_base_addr;
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struct {
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uint64_t vdm_ctx_store_task0;
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uint32_t vdm_ctx_store_task1;
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uint64_t vdm_ctx_store_task2;
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uint64_t vdm_ctx_resume_task0;
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uint32_t vdm_ctx_resume_task1;
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uint64_t vdm_ctx_resume_task2;
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} geom_state[2];
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} static_state;
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};
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struct pvr_winsys_render_ctx {
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struct pvr_winsys *ws;
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};
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struct pvr_winsys_compute_ctx_create_info {
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enum pvr_winsys_ctx_priority priority;
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struct pvr_winsys_compute_ctx_static_state {
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uint64_t cdm_ctx_store_pds0;
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uint64_t cdm_ctx_store_pds0_b;
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uint32_t cdm_ctx_store_pds1;
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uint64_t cdm_ctx_terminate_pds;
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uint32_t cdm_ctx_terminate_pds1;
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uint64_t cdm_ctx_resume_pds0;
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uint64_t cdm_ctx_resume_pds0_b;
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} static_state;
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};
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struct pvr_winsys_compute_ctx {
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struct pvr_winsys *ws;
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};
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struct pvr_winsys_transfer_ctx_create_info {
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enum pvr_winsys_ctx_priority priority;
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};
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struct pvr_winsys_transfer_ctx {
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struct pvr_winsys *ws;
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};
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#define PVR_WINSYS_TRANSFER_FLAG_START BITFIELD_BIT(0U)
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#define PVR_WINSYS_TRANSFER_FLAG_END BITFIELD_BIT(1U)
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#define PVR_TRANSFER_MAX_PREPARES_PER_SUBMIT 16U
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#define PVR_TRANSFER_MAX_RENDER_TARGETS 3U
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struct pvr_winsys_transfer_regs {
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uint32_t event_pixel_pds_code;
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uint32_t event_pixel_pds_data;
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uint32_t event_pixel_pds_info;
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uint32_t isp_aa;
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uint32_t isp_bgobjvals;
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uint32_t isp_ctl;
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uint64_t isp_mtile_base;
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uint32_t isp_mtile_size;
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uint32_t isp_render;
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uint32_t isp_render_origin;
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uint32_t isp_rgn;
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uint64_t pbe_wordx_mrty[PVR_TRANSFER_MAX_RENDER_TARGETS *
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ROGUE_NUM_PBESTATE_REG_WORDS];
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uint64_t pds_bgnd0_base;
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uint64_t pds_bgnd1_base;
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uint64_t pds_bgnd3_sizeinfo;
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uint32_t usc_clear_register0;
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uint32_t usc_clear_register1;
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uint32_t usc_clear_register2;
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uint32_t usc_clear_register3;
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uint32_t usc_pixel_output_ctrl;
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};
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struct pvr_winsys_transfer_submit_info {
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uint32_t frame_num;
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uint32_t job_num;
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struct vk_sync *barrier;
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/* waits and stage_flags are arrays of length wait_count. */
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struct vk_sync **waits;
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uint32_t wait_count;
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uint32_t *stage_flags;
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uint32_t cmd_count;
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struct {
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struct pvr_winsys_transfer_regs regs;
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/* Must be 0 or a combination of PVR_WINSYS_TRANSFER_FLAG_* flags. */
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uint32_t flags;
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} cmds[PVR_TRANSFER_MAX_PREPARES_PER_SUBMIT];
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};
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#define PVR_WINSYS_COMPUTE_FLAG_PREVENT_ALL_OVERLAP BITFIELD_BIT(0U)
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#define PVR_WINSYS_COMPUTE_FLAG_SINGLE_CORE BITFIELD_BIT(1U)
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struct pvr_winsys_compute_submit_info {
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uint32_t frame_num;
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uint32_t job_num;
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struct vk_sync *barrier;
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/* waits and stage_flags are arrays of length wait_count. */
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struct vk_sync **waits;
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uint32_t wait_count;
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uint32_t *stage_flags;
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/* Firmware stream buffer. This is the maximum possible size taking into
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* consideration all HW features.
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*/
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uint8_t fw_stream[92];
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uint32_t fw_stream_len;
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/* Firmware extension stream buffer. This is the maximum possible size taking
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* into considation all quirks and enhancements.
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*/
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uint8_t fw_ext_stream[8];
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uint32_t fw_ext_stream_len;
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/* Must be 0 or a combination of PVR_WINSYS_COMPUTE_FLAG_* flags. */
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uint32_t flags;
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};
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#define PVR_WINSYS_GEOM_FLAG_FIRST_GEOMETRY BITFIELD_BIT(0U)
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#define PVR_WINSYS_GEOM_FLAG_LAST_GEOMETRY BITFIELD_BIT(1U)
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#define PVR_WINSYS_GEOM_FLAG_SINGLE_CORE BITFIELD_BIT(2U)
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#define PVR_WINSYS_FRAG_FLAG_DEPTH_BUFFER_PRESENT BITFIELD_BIT(0U)
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#define PVR_WINSYS_FRAG_FLAG_STENCIL_BUFFER_PRESENT BITFIELD_BIT(1U)
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#define PVR_WINSYS_FRAG_FLAG_PREVENT_CDM_OVERLAP BITFIELD_BIT(2U)
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#define PVR_WINSYS_FRAG_FLAG_SINGLE_CORE BITFIELD_BIT(3U)
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struct pvr_winsys_render_submit_info {
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struct pvr_winsys_rt_dataset *rt_dataset;
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uint8_t rt_data_idx;
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uint32_t frame_num;
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uint32_t job_num;
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/* FIXME: should this be flags instead? */
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bool run_frag;
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struct vk_sync *barrier_geom;
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struct vk_sync *barrier_frag;
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/* waits and stage_flags are arrays of length wait_count. */
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struct vk_sync **waits;
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uint32_t wait_count;
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uint32_t *stage_flags;
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struct pvr_winsys_geometry_state {
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/* Firmware stream buffer. This is the maximum possible size taking into
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* consideration all HW features.
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*/
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uint8_t fw_stream[52];
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uint32_t fw_stream_len;
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/* Firmware extension stream buffer. This is the maximum possible size
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* taking into considation all quirks and enhancements.
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*/
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uint8_t fw_ext_stream[12];
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uint32_t fw_ext_stream_len;
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/* Must be 0 or a combination of PVR_WINSYS_GEOM_FLAG_* flags. */
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uint32_t flags;
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} geometry;
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struct pvr_winsys_fragment_state {
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/* Firmware stream buffer. This is the maximum possible size taking into
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* consideration all HW features.
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*/
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uint8_t fw_stream[432];
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uint32_t fw_stream_len;
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/* Firmware extension stream buffer. This is the maximum possible size
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* taking into considation all quirks and enhancements.
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*/
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uint8_t fw_ext_stream[8];
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uint32_t fw_ext_stream_len;
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/* Must be 0 or a combination of PVR_WINSYS_FRAG_FLAG_* flags. */
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uint32_t flags;
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} fragment;
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};
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struct pvr_winsys_ops {
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void (*destroy)(struct pvr_winsys *ws);
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int (*device_info_init)(struct pvr_winsys *ws,
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struct pvr_device_info *dev_info,
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struct pvr_device_runtime_info *runtime_info);
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void (*get_heaps_info)(struct pvr_winsys *ws,
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struct pvr_winsys_heaps *heaps);
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VkResult (*buffer_create)(struct pvr_winsys *ws,
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uint64_t size,
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uint64_t alignment,
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enum pvr_winsys_bo_type type,
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uint32_t flags,
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struct pvr_winsys_bo **const bo_out);
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VkResult (*buffer_create_from_fd)(struct pvr_winsys *ws,
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int fd,
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struct pvr_winsys_bo **const bo_out);
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void (*buffer_destroy)(struct pvr_winsys_bo *bo);
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VkResult (*buffer_get_fd)(struct pvr_winsys_bo *bo, int *const fd_out);
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void *(*buffer_map)(struct pvr_winsys_bo *bo);
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void (*buffer_unmap)(struct pvr_winsys_bo *bo);
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struct pvr_winsys_vma *(*heap_alloc)(struct pvr_winsys_heap *heap,
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uint64_t size,
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uint64_t alignment);
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void (*heap_free)(struct pvr_winsys_vma *vma);
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pvr_dev_addr_t (*vma_map)(struct pvr_winsys_vma *vma,
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struct pvr_winsys_bo *bo,
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uint64_t offset,
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uint64_t size);
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void (*vma_unmap)(struct pvr_winsys_vma *vma);
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VkResult (*free_list_create)(
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struct pvr_winsys *ws,
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struct pvr_winsys_vma *free_list_vma,
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uint32_t initial_num_pages,
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uint32_t max_num_pages,
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uint32_t grow_num_pages,
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uint32_t grow_threshold,
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struct pvr_winsys_free_list *parent_free_list,
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struct pvr_winsys_free_list **const free_list_out);
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void (*free_list_destroy)(struct pvr_winsys_free_list *free_list);
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VkResult (*render_target_dataset_create)(
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struct pvr_winsys *ws,
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const struct pvr_winsys_rt_dataset_create_info *create_info,
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struct pvr_winsys_rt_dataset **const rt_dataset_out);
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void (*render_target_dataset_destroy)(
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struct pvr_winsys_rt_dataset *rt_dataset);
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VkResult (*render_ctx_create)(
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struct pvr_winsys *ws,
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struct pvr_winsys_render_ctx_create_info *create_info,
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struct pvr_winsys_render_ctx **const ctx_out);
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void (*render_ctx_destroy)(struct pvr_winsys_render_ctx *ctx);
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VkResult (*render_submit)(
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const struct pvr_winsys_render_ctx *ctx,
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const struct pvr_winsys_render_submit_info *submit_info,
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const struct pvr_device_info *dev_info,
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struct vk_sync *signal_sync_geom,
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struct vk_sync *signal_sync_frag);
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VkResult (*compute_ctx_create)(
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struct pvr_winsys *ws,
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const struct pvr_winsys_compute_ctx_create_info *create_info,
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struct pvr_winsys_compute_ctx **const ctx_out);
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void (*compute_ctx_destroy)(struct pvr_winsys_compute_ctx *ctx);
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VkResult (*compute_submit)(
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const struct pvr_winsys_compute_ctx *ctx,
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const struct pvr_winsys_compute_submit_info *submit_info,
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const struct pvr_device_info *dev_info,
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struct vk_sync *signal_sync);
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VkResult (*transfer_ctx_create)(
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struct pvr_winsys *ws,
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const struct pvr_winsys_transfer_ctx_create_info *create_info,
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struct pvr_winsys_transfer_ctx **const ctx_out);
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void (*transfer_ctx_destroy)(struct pvr_winsys_transfer_ctx *ctx);
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VkResult (*transfer_submit)(
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const struct pvr_winsys_transfer_ctx *ctx,
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const struct pvr_winsys_transfer_submit_info *submit_info,
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struct vk_sync *signal_sync);
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VkResult (*null_job_submit)(struct pvr_winsys *ws,
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struct vk_sync **waits,
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uint32_t wait_count,
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struct vk_sync *signal_sync);
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};
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struct pvr_winsys {
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uint64_t page_size;
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uint32_t log2_page_size;
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const struct vk_sync_type *sync_types[2];
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struct vk_sync_type syncobj_type;
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const struct pvr_winsys_ops *ops;
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};
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void pvr_winsys_destroy(struct pvr_winsys *ws);
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struct pvr_winsys *pvr_winsys_create(int master_fd,
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int render_fd,
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const VkAllocationCallbacks *alloc);
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#endif /* PVR_WINSYS_H */
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