mirror of https://gitlab.freedesktop.org/mesa/mesa
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/*
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* Copyright © 2019 Valve Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_SHADER_ARGS_H
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#define RADV_SHADER_ARGS_H
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#include "compiler/shader_enums.h"
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#include "util/list.h"
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#include "util/macros.h"
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#include "ac_shader_args.h"
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#include "amd_family.h"
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#include "radv_constants.h"
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#include "radv_shader.h"
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struct radv_shader_args {
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struct ac_shader_args ac;
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struct ac_arg descriptor_sets[MAX_SETS];
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/* User data 0/1. GFX: descriptor list, Compute: scratch BO */
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struct ac_arg ring_offsets;
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/* User data 2/3. same as the descriptor list above but for task shaders. */
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struct ac_arg task_ring_offsets;
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/* Streamout */
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struct ac_arg streamout_buffers;
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/* NGG */
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struct ac_arg ngg_query_state;
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struct ac_arg ngg_provoking_vtx;
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/* NGG GS */
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struct ac_arg ngg_culling_settings;
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struct ac_arg ngg_viewport_scale[2];
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struct ac_arg ngg_viewport_translate[2];
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/* Task shaders */
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struct ac_arg task_ib_addr;
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struct ac_arg task_ib_stride;
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/* Fragment shaders */
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struct ac_arg ps_epilog_pc;
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struct ac_arg ps_num_samples;
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struct ac_arg prolog_inputs;
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struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS];
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/* PS epilogs */
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struct ac_arg ps_epilog_inputs[MAX_RTS];
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/* TCS */
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/* # [0:5] = the number of patch control points
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* # [6:13] = the number of tessellation patches
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*/
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struct ac_arg tcs_offchip_layout;
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/* TES */
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struct ac_arg tes_num_patches;
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struct radv_userdata_locations user_sgprs_locs;
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unsigned num_user_sgprs;
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bool explicit_scratch_args;
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bool remap_spi_ps_input;
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bool load_grid_size_from_user_sgpr;
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bool is_gs_copy_shader;
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bool is_trap_handler_shader;
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};
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static inline struct radv_shader_args *
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radv_shader_args_from_ac(struct ac_shader_args *args)
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{
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return container_of(args, struct radv_shader_args, ac);
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}
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struct radv_pipeline_key;
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struct radv_shader_info;
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void radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipeline_key *key,
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const struct radv_shader_info *info, gl_shader_stage stage,
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bool has_previous_stage, gl_shader_stage previous_stage,
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struct radv_shader_args *args);
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void radv_declare_ps_epilog_args(enum amd_gfx_level gfx_level, const struct radv_ps_epilog_key *key,
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struct radv_shader_args *args);
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#endif
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