mirror of https://gitlab.freedesktop.org/mesa/mesa
1050 lines
43 KiB
C
1050 lines
43 KiB
C
/*
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* Copyright © 2016 Dave Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "nir/nir_builder.h"
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "sid.h"
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#include "vk_format.h"
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static nir_shader *
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build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samples)
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{
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enum glsl_base_type img_base_type = is_integer ? GLSL_TYPE_UINT : GLSL_TYPE_FLOAT;
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const struct glsl_type *vec4 = glsl_vec4_type();
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const struct glsl_type *sampler_type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, img_base_type);
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs-%d-%s",
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samples, is_integer ? "int" : "float");
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "f_color");
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color_out->data.location = FRAG_RESULT_DATA0;
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nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
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nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, src_offset), 0x3);
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nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
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radv_meta_build_resolve_shader_core(dev, &b, is_integer, samples, input_img, color, img_coord);
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nir_ssa_def *outval = nir_load_var(&b, color);
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nir_store_var(&b, color_out, outval, 0xf);
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return b.shader;
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}
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static VkResult
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create_layout(struct radv_device *device)
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{
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VkResult result;
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/*
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* one descriptors for the image being sampled
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 1,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_fragment.ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.resolve_fragment.ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 8},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_fragment.p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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return VK_SUCCESS;
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fail:
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return result;
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}
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static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
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.vertexBindingDescriptionCount = 0,
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.vertexAttributeDescriptionCount = 0,
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};
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static VkResult
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create_resolve_pipeline(struct radv_device *device, int samples_log2, VkFormat format)
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{
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mtx_lock(&device->meta_state.mtx);
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unsigned fs_key = radv_format_meta_fs_key(device, format);
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VkPipeline *pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
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if (*pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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VkResult result;
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bool is_integer = false;
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uint32_t samples = 1 << samples_log2;
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const VkPipelineVertexInputStateCreateInfo *vi_create_info;
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vi_create_info = &normal_vi_create_info;
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if (vk_format_is_int(format))
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is_integer = true;
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nir_shader *fs = build_resolve_fragment_shader(device, is_integer, samples);
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nir_shader *vs = radv_meta_build_nir_vs_generate_vertices(device);
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VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
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{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = vk_shader_module_handle_from_nir(vs),
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.pName = "main",
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.pSpecializationInfo = NULL},
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{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = vk_shader_module_handle_from_nir(fs),
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.pName = "main",
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.pSpecializationInfo = NULL},
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};
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const VkPipelineRenderingCreateInfo rendering_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
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.colorAttachmentCount = 1,
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.pColorAttachmentFormats = &format,
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};
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const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
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.pNext = &rendering_create_info,
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.stageCount = ARRAY_SIZE(pipeline_shader_stages),
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.pStages = pipeline_shader_stages,
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.pVertexInputState = vi_create_info,
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.pInputAssemblyState =
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&(VkPipelineInputAssemblyStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
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.primitiveRestartEnable = false,
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},
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.pViewportState =
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&(VkPipelineViewportStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
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.viewportCount = 1,
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.scissorCount = 1,
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},
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.pRasterizationState =
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&(VkPipelineRasterizationStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
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.rasterizerDiscardEnable = false,
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.polygonMode = VK_POLYGON_MODE_FILL,
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.cullMode = VK_CULL_MODE_NONE,
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.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
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.depthBiasConstantFactor = 0.0f,
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.depthBiasClamp = 0.0f,
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.depthBiasSlopeFactor = 0.0f,
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.lineWidth = 1.0f},
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.pMultisampleState =
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&(VkPipelineMultisampleStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
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.rasterizationSamples = 1,
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.sampleShadingEnable = false,
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.pSampleMask = (VkSampleMask[]){UINT32_MAX},
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},
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.pColorBlendState =
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&(VkPipelineColorBlendStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
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.attachmentCount = 1,
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.pAttachments =
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(VkPipelineColorBlendAttachmentState[]){
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{.colorWriteMask = VK_COLOR_COMPONENT_A_BIT | VK_COLOR_COMPONENT_R_BIT |
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VK_COLOR_COMPONENT_G_BIT | VK_COLOR_COMPONENT_B_BIT},
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},
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.blendConstants = { 0.0f, 0.0f, 0.0f, 0.0f }},
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.pDynamicState =
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&(VkPipelineDynamicStateCreateInfo){
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
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.dynamicStateCount = 2,
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.pDynamicStates =
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(VkDynamicState[]){
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VK_DYNAMIC_STATE_VIEWPORT,
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VK_DYNAMIC_STATE_SCISSOR,
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},
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},
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.flags = 0,
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.layout = device->meta_state.resolve_fragment.p_layout,
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.renderPass = VK_NULL_HANDLE,
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.subpass = 0,
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};
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const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true};
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result = radv_graphics_pipeline_create(
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radv_device_to_handle(device), device->meta_state.cache,
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&vk_pipeline_info, &radv_pipeline_info, &device->meta_state.alloc, pipeline);
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ralloc_free(vs);
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ralloc_free(fs);
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mtx_unlock(&device->meta_state.mtx);
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return result;
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}
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enum { DEPTH_RESOLVE, STENCIL_RESOLVE };
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static const char *
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get_resolve_mode_str(VkResolveModeFlagBits resolve_mode)
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{
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
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return "zero";
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case VK_RESOLVE_MODE_AVERAGE_BIT:
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return "average";
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case VK_RESOLVE_MODE_MIN_BIT:
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return "min";
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case VK_RESOLVE_MODE_MAX_BIT:
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return "max";
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default:
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unreachable("invalid resolve mode");
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}
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}
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static nir_shader *
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build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples, int index,
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VkResolveModeFlagBits resolve_mode)
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{
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enum glsl_base_type img_base_type = index == DEPTH_RESOLVE ? GLSL_TYPE_FLOAT : GLSL_TYPE_UINT;
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const struct glsl_type *vec4 = glsl_vec4_type();
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const struct glsl_type *sampler_type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, img_base_type);
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_FRAGMENT, "meta_resolve_fs_%s-%s-%d",
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index == DEPTH_RESOLVE ? "depth" : "stencil",
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get_resolve_mode_str(resolve_mode), samples);
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *fs_out = nir_variable_create(b.shader, nir_var_shader_out, vec4, "f_out");
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fs_out->data.location = index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
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nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
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nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
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nir_ssa_def *img_coord = nir_channels(&b, pos_int, 0x3);
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float32 : nir_type_uint32;
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(img_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = type;
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tex->is_array = false;
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tex->coord_components = 2;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_ssa_def *outval = &tex->dest.ssa;
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if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT) {
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for (int i = 1; i < samples; i++) {
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nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
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tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_add->op = nir_texop_txf_ms;
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tex_add->src[0].src_type = nir_tex_src_coord;
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tex_add->src[0].src = nir_src_for_ssa(img_coord);
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tex_add->src[1].src_type = nir_tex_src_ms_index;
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tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex_add->src[2].src_type = nir_tex_src_texture_deref;
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tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
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tex_add->dest_type = type;
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tex_add->is_array = false;
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tex_add->coord_components = 2;
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nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex_add->instr);
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_AVERAGE_BIT:
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assert(index == DEPTH_RESOLVE);
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outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
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break;
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case VK_RESOLVE_MODE_MIN_BIT:
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if (index == DEPTH_RESOLVE)
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outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umin(&b, outval, &tex_add->dest.ssa);
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break;
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case VK_RESOLVE_MODE_MAX_BIT:
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if (index == DEPTH_RESOLVE)
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outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umax(&b, outval, &tex_add->dest.ssa);
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break;
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default:
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unreachable("invalid resolve mode");
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}
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}
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if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT)
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outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
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}
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nir_store_var(&b, fs_out, outval, 0x1);
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return b.shader;
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}
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static VkResult
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create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples_log2, int index,
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VkResolveModeFlagBits resolve_mode)
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{
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VkPipeline *pipeline;
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VkResult result;
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mtx_lock(&device->meta_state.mtx);
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switch (resolve_mode) {
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
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break;
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case VK_RESOLVE_MODE_AVERAGE_BIT:
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assert(index == DEPTH_RESOLVE);
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
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break;
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case VK_RESOLVE_MODE_MIN_BIT:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
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break;
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case VK_RESOLVE_MODE_MAX_BIT:
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if (index == DEPTH_RESOLVE)
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pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
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else
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pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
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break;
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default:
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unreachable("invalid resolve mode");
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}
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if (*pipeline) {
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mtx_unlock(&device->meta_state.mtx);
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return VK_SUCCESS;
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}
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uint32_t samples = 1 << samples_log2;
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nir_shader *fs =
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build_depth_stencil_resolve_fragment_shader(device, samples, index, resolve_mode);
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nir_shader *vs = radv_meta_build_nir_vs_generate_vertices(device);
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VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
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{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_VERTEX_BIT,
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.module = vk_shader_module_handle_from_nir(vs),
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.pName = "main",
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.pSpecializationInfo = NULL},
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{.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_FRAGMENT_BIT,
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.module = vk_shader_module_handle_from_nir(fs),
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.pName = "main",
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.pSpecializationInfo = NULL},
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};
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VkStencilOp stencil_op = index == DEPTH_RESOLVE ? VK_STENCIL_OP_KEEP : VK_STENCIL_OP_REPLACE;
|
|
|
|
VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
|
|
.depthTestEnable = true,
|
|
.depthWriteEnable = index == DEPTH_RESOLVE,
|
|
.stencilTestEnable = index == STENCIL_RESOLVE,
|
|
.depthCompareOp = VK_COMPARE_OP_ALWAYS,
|
|
.front =
|
|
{
|
|
.failOp = stencil_op,
|
|
.passOp = stencil_op,
|
|
.depthFailOp = stencil_op,
|
|
.compareOp = VK_COMPARE_OP_ALWAYS,
|
|
.compareMask = UINT32_MAX,
|
|
.writeMask = UINT32_MAX,
|
|
.reference = 0u,
|
|
},
|
|
.back = {
|
|
.failOp = stencil_op,
|
|
.passOp = stencil_op,
|
|
.depthFailOp = stencil_op,
|
|
.compareOp = VK_COMPARE_OP_ALWAYS,
|
|
.compareMask = UINT32_MAX,
|
|
.writeMask = UINT32_MAX,
|
|
.reference = 0u,
|
|
},
|
|
.minDepthBounds = 0.0f,
|
|
.maxDepthBounds = 1.0f};
|
|
|
|
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
|
|
vi_create_info = &normal_vi_create_info;
|
|
|
|
const VkPipelineRenderingCreateInfo rendering_create_info = {
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO,
|
|
.depthAttachmentFormat = index == DEPTH_RESOLVE ? VK_FORMAT_D32_SFLOAT : VK_FORMAT_UNDEFINED,
|
|
.stencilAttachmentFormat = index == STENCIL_RESOLVE ? VK_FORMAT_S8_UINT : VK_FORMAT_UNDEFINED,
|
|
};
|
|
|
|
const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
|
|
.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
|
|
.pNext = &rendering_create_info,
|
|
.stageCount = ARRAY_SIZE(pipeline_shader_stages),
|
|
.pStages = pipeline_shader_stages,
|
|
.pVertexInputState = vi_create_info,
|
|
.pInputAssemblyState =
|
|
&(VkPipelineInputAssemblyStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
|
|
.topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
|
|
.primitiveRestartEnable = false,
|
|
},
|
|
.pViewportState =
|
|
&(VkPipelineViewportStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
|
|
.viewportCount = 1,
|
|
.scissorCount = 1,
|
|
},
|
|
.pDepthStencilState = &depth_stencil_state,
|
|
.pRasterizationState =
|
|
&(VkPipelineRasterizationStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
|
|
.rasterizerDiscardEnable = false,
|
|
.polygonMode = VK_POLYGON_MODE_FILL,
|
|
.cullMode = VK_CULL_MODE_NONE,
|
|
.frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
|
|
.depthBiasConstantFactor = 0.0f,
|
|
.depthBiasClamp = 0.0f,
|
|
.depthBiasSlopeFactor = 0.0f,
|
|
.lineWidth = 1.0f},
|
|
.pMultisampleState =
|
|
&(VkPipelineMultisampleStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
|
|
.rasterizationSamples = 1,
|
|
.sampleShadingEnable = false,
|
|
.pSampleMask = (VkSampleMask[]){UINT32_MAX},
|
|
},
|
|
.pColorBlendState =
|
|
&(VkPipelineColorBlendStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
|
|
.attachmentCount = 0,
|
|
.pAttachments =
|
|
(VkPipelineColorBlendAttachmentState[]){
|
|
{.colorWriteMask = VK_COLOR_COMPONENT_A_BIT | VK_COLOR_COMPONENT_R_BIT |
|
|
VK_COLOR_COMPONENT_G_BIT | VK_COLOR_COMPONENT_B_BIT},
|
|
},
|
|
.blendConstants = { 0.0f, 0.0f, 0.0f, 0.0f }},
|
|
.pDynamicState =
|
|
&(VkPipelineDynamicStateCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
|
|
.dynamicStateCount = 2,
|
|
.pDynamicStates =
|
|
(VkDynamicState[]){
|
|
VK_DYNAMIC_STATE_VIEWPORT,
|
|
VK_DYNAMIC_STATE_SCISSOR,
|
|
},
|
|
},
|
|
.flags = 0,
|
|
.layout = device->meta_state.resolve_fragment.p_layout,
|
|
.renderPass = VK_NULL_HANDLE,
|
|
.subpass = 0,
|
|
};
|
|
|
|
const struct radv_graphics_pipeline_create_info radv_pipeline_info = {.use_rectlist = true};
|
|
|
|
result = radv_graphics_pipeline_create(
|
|
radv_device_to_handle(device), device->meta_state.cache,
|
|
&vk_pipeline_info, &radv_pipeline_info, &device->meta_state.alloc, pipeline);
|
|
|
|
ralloc_free(vs);
|
|
ralloc_free(fs);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
return result;
|
|
}
|
|
|
|
VkResult
|
|
radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on_demand)
|
|
{
|
|
VkResult res;
|
|
|
|
res = create_layout(device);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
if (on_demand)
|
|
return VK_SUCCESS;
|
|
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
|
res = create_resolve_pipeline(device, i, radv_fs_key_format_exemplars[j]);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
}
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_AVERAGE_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_MIN_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_MAX_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_MIN_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_MAX_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
}
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
|
|
if (res != VK_SUCCESS)
|
|
return res;
|
|
|
|
return create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
|
|
}
|
|
|
|
void
|
|
radv_device_finish_meta_resolve_fragment_state(struct radv_device *device)
|
|
{
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.rc[i].pipeline[j], &state->alloc);
|
|
}
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].average_pipeline, &state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].max_pipeline, &state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.depth[i].min_pipeline, &state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil[i].max_pipeline, &state->alloc);
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil[i].min_pipeline, &state->alloc);
|
|
}
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device), state->resolve_fragment.depth_zero_pipeline,
|
|
&state->alloc);
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
state->resolve_fragment.stencil_zero_pipeline, &state->alloc);
|
|
|
|
device->vk.dispatch_table.DestroyDescriptorSetLayout(
|
|
radv_device_to_handle(device), state->resolve_fragment.ds_layout, &state->alloc);
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device), state->resolve_fragment.p_layout,
|
|
&state->alloc);
|
|
}
|
|
|
|
static VkPipeline *
|
|
radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
|
|
struct radv_image_view *dst_iview)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
unsigned fs_key = radv_format_meta_fs_key(cmd_buffer->device, dst_iview->vk.format);
|
|
const uint32_t samples = src_iview->image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
VkPipeline *pipeline;
|
|
|
|
pipeline = &device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
|
|
if (!*pipeline) {
|
|
VkResult ret;
|
|
|
|
ret = create_resolve_pipeline(device, samples_log2, radv_fs_key_format_exemplars[fs_key]);
|
|
if (ret != VK_SUCCESS) {
|
|
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
return pipeline;
|
|
}
|
|
|
|
static void
|
|
emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
|
|
struct radv_image_view *dest_iview, const VkOffset2D *src_offset,
|
|
const VkOffset2D *dest_offset)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
|
|
VkPipeline *pipeline;
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
cmd_buffer->device->meta_state.resolve_fragment.p_layout,
|
|
0, /* set */
|
|
1, /* descriptorWriteCount */
|
|
(VkWriteDescriptorSet[]){
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 0,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
.pImageInfo =
|
|
(VkDescriptorImageInfo[]){
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}},
|
|
});
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, src_iview->image) |
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
|
|
|
|
unsigned push_constants[2] = {
|
|
src_offset->x - dest_offset->x,
|
|
src_offset->y - dest_offset->y,
|
|
};
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
device->meta_state.resolve_fragment.p_layout, VK_SHADER_STAGE_FRAGMENT_BIT,
|
|
0, 8, push_constants);
|
|
|
|
pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview, dest_iview);
|
|
|
|
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, *pipeline);
|
|
|
|
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
|
|
cmd_buffer->state.flush_bits |=
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
|
|
}
|
|
|
|
static void
|
|
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
|
|
struct radv_image_view *dst_iview, const VkOffset2D *resolve_offset,
|
|
const VkExtent2D *resolve_extent, VkImageAspectFlags aspects,
|
|
VkResolveModeFlagBits resolve_mode)
|
|
{
|
|
struct radv_device *device = cmd_buffer->device;
|
|
const uint32_t samples = src_iview->image->info.samples;
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
VkPipeline *pipeline;
|
|
|
|
radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
cmd_buffer->device->meta_state.resolve_fragment.p_layout,
|
|
0, /* set */
|
|
1, /* descriptorWriteCount */
|
|
(VkWriteDescriptorSet[]){
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
.dstBinding = 0,
|
|
.dstArrayElement = 0,
|
|
.descriptorCount = 1,
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
.pImageInfo =
|
|
(VkDescriptorImageInfo[]){
|
|
{
|
|
.sampler = VK_NULL_HANDLE,
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
},
|
|
}},
|
|
});
|
|
|
|
switch (resolve_mode) {
|
|
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_AVERAGE_BIT:
|
|
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MIN_BIT:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
|
|
break;
|
|
case VK_RESOLVE_MODE_MAX_BIT:
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
|
|
else
|
|
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].max_pipeline;
|
|
break;
|
|
default:
|
|
unreachable("invalid resolve mode");
|
|
}
|
|
|
|
if (!*pipeline) {
|
|
int index = aspects == VK_IMAGE_ASPECT_DEPTH_BIT ? DEPTH_RESOLVE : STENCIL_RESOLVE;
|
|
VkResult ret;
|
|
|
|
ret = create_depth_stencil_resolve_pipeline(device, samples_log2, index, resolve_mode);
|
|
if (ret != VK_SUCCESS) {
|
|
vk_command_buffer_set_error(&cmd_buffer->vk, ret);
|
|
return;
|
|
}
|
|
}
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
|
|
*pipeline);
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkViewport){.x = resolve_offset->x,
|
|
.y = resolve_offset->y,
|
|
.width = resolve_extent->width,
|
|
.height = resolve_extent->height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkRect2D){
|
|
.offset = *resolve_offset,
|
|
.extent = *resolve_extent,
|
|
});
|
|
|
|
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
|
|
}
|
|
|
|
void
|
|
radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
|
|
VkImageLayout src_image_layout, struct radv_image *dest_image,
|
|
VkImageLayout dest_image_layout, const VkImageResolve2 *region)
|
|
{
|
|
struct radv_meta_saved_state saved_state;
|
|
unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
|
|
VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
|
|
|
|
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout, region);
|
|
|
|
radv_meta_save(
|
|
&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
|
|
|
|
const uint32_t src_base_layer =
|
|
radv_meta_get_iview_layer(src_image, ®ion->srcSubresource, ®ion->srcOffset);
|
|
|
|
const uint32_t dest_base_layer =
|
|
radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource, ®ion->dstOffset);
|
|
|
|
const struct VkExtent3D extent = vk_image_sanitize_extent(&src_image->vk, region->extent);
|
|
const struct VkOffset3D srcOffset = vk_image_sanitize_offset(&src_image->vk, region->srcOffset);
|
|
const struct VkOffset3D dstOffset = vk_image_sanitize_offset(&dest_image->vk, region->dstOffset);
|
|
|
|
VkRect2D resolve_area = {
|
|
.offset = { dstOffset.x, dstOffset.y },
|
|
.extent = { extent.width, extent.height },
|
|
};
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkViewport){.x = resolve_area.offset.x,
|
|
.y = resolve_area.offset.y,
|
|
.width = resolve_area.extent.width,
|
|
.height = resolve_area.extent.height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &resolve_area);
|
|
|
|
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount; ++layer) {
|
|
|
|
struct radv_image_view src_iview;
|
|
radv_image_view_init(&src_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(src_image),
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
.format = src_image->vk.format,
|
|
.subresourceRange =
|
|
{
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = region->srcSubresource.mipLevel,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = src_base_layer + layer,
|
|
.layerCount = 1,
|
|
},
|
|
},
|
|
0, NULL);
|
|
|
|
struct radv_image_view dest_iview;
|
|
radv_image_view_init(&dest_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(dest_image),
|
|
.viewType = radv_meta_get_view_type(dest_image),
|
|
.format = dest_image->vk.format,
|
|
.subresourceRange =
|
|
{
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = dest_base_layer + layer,
|
|
.layerCount = 1,
|
|
},
|
|
},
|
|
0, NULL);
|
|
|
|
const VkRenderingAttachmentInfo color_att = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
.imageView = radv_image_view_to_handle(&dest_iview),
|
|
.imageLayout = layout,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
};
|
|
|
|
const VkRenderingInfo rendering_info = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
|
|
.renderArea = resolve_area,
|
|
.layerCount = 1,
|
|
.colorAttachmentCount = 1,
|
|
.pColorAttachments = &color_att,
|
|
};
|
|
|
|
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
|
|
|
|
emit_resolve(cmd_buffer, &src_iview, &dest_iview, &(VkOffset2D){srcOffset.x, srcOffset.y},
|
|
&(VkOffset2D){dstOffset.x, dstOffset.y});
|
|
|
|
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
|
|
radv_image_view_finish(&src_iview);
|
|
radv_image_view_finish(&dest_iview);
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|
|
|
|
/**
|
|
* Emit any needed resolves for the current rendering.
|
|
*/
|
|
void
|
|
radv_cmd_buffer_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer)
|
|
{
|
|
struct radv_meta_saved_state saved_state;
|
|
struct radv_resolve_barrier barrier;
|
|
|
|
/* Resolves happen before rendering ends, so we have to make the attachment shader-readable */
|
|
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
|
|
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
|
|
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
|
|
radv_emit_resolve_barrier(cmd_buffer, &barrier);
|
|
|
|
radv_decompress_resolve_rendering_src(cmd_buffer);
|
|
|
|
radv_meta_save(
|
|
&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS |
|
|
RADV_META_SAVE_RENDER);
|
|
|
|
VkRect2D *resolve_area = &saved_state.render.area;
|
|
|
|
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
|
|
&(VkViewport){.x = resolve_area->offset.x,
|
|
.y = resolve_area->offset.y,
|
|
.width = resolve_area->extent.width,
|
|
.height = resolve_area->extent.height,
|
|
.minDepth = 0.0f,
|
|
.maxDepth = 1.0f});
|
|
|
|
radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, resolve_area);
|
|
|
|
for (uint32_t i = 0; i < saved_state.render.color_att_count; ++i) {
|
|
if (saved_state.render.color_att[i].resolve_iview == NULL)
|
|
continue;
|
|
|
|
struct radv_image_view *src_iview = saved_state.render.color_att[i].iview;
|
|
struct radv_image_view *dst_iview = saved_state.render.color_att[i].resolve_iview;
|
|
|
|
const VkRenderingAttachmentInfo color_att = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
.imageView = radv_image_view_to_handle(dst_iview),
|
|
.imageLayout = saved_state.render.color_att[i].resolve_layout,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
};
|
|
|
|
const VkRenderingInfo rendering_info = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
|
|
.renderArea = saved_state.render.area,
|
|
.layerCount = saved_state.render.layer_count,
|
|
.viewMask = saved_state.render.view_mask,
|
|
.colorAttachmentCount = 1,
|
|
.pColorAttachments = &color_att,
|
|
};
|
|
|
|
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
|
|
|
|
emit_resolve(cmd_buffer, src_iview, dst_iview, &saved_state.render.area.offset,
|
|
&saved_state.render.area.offset);
|
|
|
|
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
}
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|
|
|
|
/**
|
|
* Depth/stencil resolves for the current rendering.
|
|
*/
|
|
void
|
|
radv_depth_stencil_resolve_rendering_fs(struct radv_cmd_buffer *cmd_buffer,
|
|
VkImageAspectFlags aspects,
|
|
VkResolveModeFlagBits resolve_mode)
|
|
{
|
|
const struct radv_rendering_state *render = &cmd_buffer->state.render;
|
|
VkRect2D resolve_area = render->area;
|
|
struct radv_meta_saved_state saved_state;
|
|
struct radv_resolve_barrier barrier;
|
|
|
|
/* Resolves happen before rendering ends, so we have to make the attachment shader-readable */
|
|
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
|
|
barrier.src_access_mask = VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
|
|
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
|
|
radv_emit_resolve_barrier(cmd_buffer, &barrier);
|
|
|
|
struct radv_image_view *src_iview = cmd_buffer->state.render.ds_att.iview;
|
|
VkImageLayout src_layout = cmd_buffer->state.render.ds_att.layout;
|
|
struct radv_image *src_image = src_iview->image;
|
|
|
|
VkImageResolve2 region = {0};
|
|
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
|
|
region.srcSubresource.aspectMask = aspects;
|
|
region.srcSubresource.mipLevel = 0;
|
|
region.srcSubresource.baseArrayLayer = 0;
|
|
region.srcSubresource.layerCount = 1;
|
|
|
|
radv_decompress_resolve_src(cmd_buffer, src_image, src_layout, ®ion);
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_DESCRIPTORS |
|
|
RADV_META_SAVE_RENDER);
|
|
|
|
struct radv_image_view *dst_iview = saved_state.render.ds_att.resolve_iview;
|
|
|
|
const VkRenderingAttachmentInfo depth_att = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
.imageView = radv_image_view_to_handle(dst_iview),
|
|
.imageLayout = saved_state.render.ds_att.resolve_layout,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
};
|
|
|
|
const VkRenderingAttachmentInfo stencil_att = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
|
|
.imageView = radv_image_view_to_handle(dst_iview),
|
|
.imageLayout = saved_state.render.ds_att.stencil_resolve_layout,
|
|
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
|
|
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
|
|
};
|
|
|
|
const VkRenderingInfo rendering_info = {
|
|
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
|
|
.renderArea = saved_state.render.area,
|
|
.layerCount = saved_state.render.layer_count,
|
|
.viewMask = saved_state.render.view_mask,
|
|
.pDepthAttachment = (dst_iview->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) ?
|
|
&depth_att : NULL,
|
|
.pStencilAttachment = (dst_iview->image->vk.aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ?
|
|
&stencil_att : NULL,
|
|
};
|
|
|
|
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
|
|
|
|
struct radv_image_view tsrc_iview;
|
|
radv_image_view_init(&tsrc_iview, cmd_buffer->device,
|
|
&(VkImageViewCreateInfo){
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
.image = radv_image_to_handle(src_image),
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
.format = src_iview->vk.format,
|
|
.subresourceRange =
|
|
{
|
|
.aspectMask = aspects,
|
|
.baseMipLevel = 0,
|
|
.levelCount = 1,
|
|
.baseArrayLayer = 0,
|
|
.layerCount = 1,
|
|
},
|
|
},
|
|
0, NULL);
|
|
|
|
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview, &resolve_area.offset,
|
|
&resolve_area.extent, aspects, resolve_mode);
|
|
|
|
radv_CmdEndRendering(radv_cmd_buffer_to_handle(cmd_buffer));
|
|
|
|
radv_image_view_finish(&tsrc_iview);
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
}
|