mirror of https://gitlab.freedesktop.org/mesa/mesa
266 lines
11 KiB
C
266 lines
11 KiB
C
/*
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* Copyright © 2019 Valve Corporation
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* Copyright © 2018 Red Hat
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "vk_format.h"
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static nir_shader *
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build_fmask_expand_compute_shader(struct radv_device *device, int samples)
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{
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const struct glsl_type *type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, true, GLSL_TYPE_FLOAT);
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nir_builder b =
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radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_fmask_expand_cs-%d", samples);
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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output_img->data.access = ACCESS_NON_READABLE;
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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nir_ssa_def *output_img_deref = &nir_build_deref_var(&b, output_img)->dest.ssa;
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nir_ssa_def *tex_coord = get_global_ids(&b, 3);
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nir_tex_instr *tex_instr[8];
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for (uint32_t i = 0; i < samples; i++) {
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tex_instr[i] = nir_tex_instr_create(b.shader, 3);
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nir_tex_instr *tex = tex_instr[i];
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(tex_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = nir_type_float32;
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tex->is_array = true;
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tex->coord_components = 3;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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}
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nir_ssa_def *img_coord =
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nir_vec4(&b, nir_channel(&b, tex_coord, 0), nir_channel(&b, tex_coord, 1),
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nir_channel(&b, tex_coord, 2), nir_ssa_undef(&b, 1, 32));
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for (uint32_t i = 0; i < samples; i++) {
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nir_ssa_def *outval = &tex_instr[i]->dest.ssa;
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nir_image_deref_store(&b, output_img_deref, img_coord, nir_imm_int(&b, i), outval,
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nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_MS, .image_array = true);
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}
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return b.shader;
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}
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void
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radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *subresourceRange)
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{
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struct radv_device *device = cmd_buffer->device;
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struct radv_meta_saved_state saved_state;
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const uint32_t samples = image->info.samples;
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const uint32_t samples_log2 = ffs(samples) - 1;
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unsigned layer_count = radv_get_layerCount(image, subresourceRange);
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struct radv_image_view iview;
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radv_meta_save(&saved_state, cmd_buffer,
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RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS);
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VkPipeline pipeline = device->meta_state.fmask_expand.pipeline[samples_log2];
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
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pipeline);
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cmd_buffer->state.flush_bits |= radv_dst_access_flush(
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cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_SHADER_WRITE_BIT, image);
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radv_image_view_init(&iview, device,
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&(VkImageViewCreateInfo){
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.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
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.image = radv_image_to_handle(image),
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.viewType = radv_meta_get_view_type(image),
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.format = vk_format_no_srgb(image->vk.format),
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.subresourceRange =
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{
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.aspectMask = subresourceRange->aspectMask,
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.baseMipLevel = 0,
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.levelCount = 1,
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.baseArrayLayer = subresourceRange->baseArrayLayer,
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.layerCount = layer_count,
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},
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},
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0, NULL);
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
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cmd_buffer->device->meta_state.fmask_expand.p_layout, 0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo =
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(VkDescriptorImageInfo[]){
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{.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
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}},
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]){
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{.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(&iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
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}}});
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radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, layer_count);
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radv_image_view_finish(&iview);
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radv_meta_restore(&saved_state, cmd_buffer);
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cmd_buffer->state.flush_bits |=
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RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
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radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
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/* Re-initialize FMASK in fully expanded mode. */
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cmd_buffer->state.flush_bits |= radv_init_fmask(cmd_buffer, image, subresourceRange);
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}
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void
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radv_device_finish_meta_fmask_expand_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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radv_DestroyPipeline(radv_device_to_handle(device), state->fmask_expand.pipeline[i],
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&state->alloc);
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}
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radv_DestroyPipelineLayout(radv_device_to_handle(device), state->fmask_expand.p_layout,
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&state->alloc);
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device->vk.dispatch_table.DestroyDescriptorSetLayout(
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radv_device_to_handle(device), state->fmask_expand.ds_layout, &state->alloc);
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}
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static VkResult
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create_fmask_expand_pipeline(struct radv_device *device, int samples, VkPipeline *pipeline)
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{
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struct radv_meta_state *state = &device->meta_state;
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VkResult result;
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nir_shader *cs = build_fmask_expand_compute_shader(device, samples);
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;
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = vk_shader_module_handle_from_nir(cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = state->fmask_expand.p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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state->cache, 1,
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&vk_pipeline_info, NULL, pipeline);
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ralloc_free(cs);
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return result;
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}
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VkResult
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radv_device_init_meta_fmask_expand_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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VkResult result;
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
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&state->alloc, &state->fmask_expand.ds_layout);
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if (result != VK_SUCCESS)
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return result;
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VkPipelineLayoutCreateInfo color_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &state->fmask_expand.ds_layout,
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.pushConstantRangeCount = 0,
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.pPushConstantRanges = NULL,
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device), &color_create_info,
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&state->alloc, &state->fmask_expand.p_layout);
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if (result != VK_SUCCESS)
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return result;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
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uint32_t samples = 1 << i;
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result = create_fmask_expand_pipeline(device, samples, &state->fmask_expand.pipeline[i]);
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if (result != VK_SUCCESS)
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return result;
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}
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return VK_SUCCESS;
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}
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