mirror of https://gitlab.freedesktop.org/mesa/mesa
544 lines
18 KiB
C
544 lines
18 KiB
C
#include "radv_meta.h"
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#include "nir/nir_builder.h"
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#include "sid.h"
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#include "radv_cs.h"
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static nir_shader *
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build_buffer_fill_shader(struct radv_device *dev)
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{
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nir_builder b;
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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b.shader->info->name = ralloc_strdup(b.shader, "meta_buffer_fill");
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b.shader->info->cs.local_size[0] = 64;
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b.shader->info->cs.local_size[1] = 1;
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b.shader->info->cs.local_size[2] = 1;
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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b.shader->info->cs.local_size[0],
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b.shader->info->cs.local_size[1],
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b.shader->info->cs.local_size[2], 0);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
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offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
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nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_vulkan_resource_index);
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dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_desc_set(dst_buf, 0);
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nir_intrinsic_set_binding(dst_buf, 0);
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nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
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nir_builder_instr_insert(&b, &dst_buf->instr);
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nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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load->num_components = 1;
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nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, "fill_value");
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nir_builder_instr_insert(&b, &load->instr);
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nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4, false);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
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store->src[0] = nir_src_for_ssa(swizzled_load);
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store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
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store->src[2] = nir_src_for_ssa(offset);
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nir_intrinsic_set_write_mask(store, 0xf);
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store->num_components = 4;
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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static nir_shader *
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build_buffer_copy_shader(struct radv_device *dev)
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{
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nir_builder b;
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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b.shader->info->name = ralloc_strdup(b.shader, "meta_buffer_copy");
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b.shader->info->cs.local_size[0] = 64;
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b.shader->info->cs.local_size[1] = 1;
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b.shader->info->cs.local_size[2] = 1;
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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b.shader->info->cs.local_size[0],
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b.shader->info->cs.local_size[1],
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b.shader->info->cs.local_size[2], 0);
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
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offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
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nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_vulkan_resource_index);
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dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_desc_set(dst_buf, 0);
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nir_intrinsic_set_binding(dst_buf, 0);
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nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL);
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nir_builder_instr_insert(&b, &dst_buf->instr);
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nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
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nir_intrinsic_vulkan_resource_index);
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src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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nir_intrinsic_set_desc_set(src_buf, 0);
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nir_intrinsic_set_binding(src_buf, 1);
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nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL);
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nir_builder_instr_insert(&b, &src_buf->instr);
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nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
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load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
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load->src[1] = nir_src_for_ssa(offset);
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nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
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load->num_components = 4;
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nir_builder_instr_insert(&b, &load->instr);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
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store->src[0] = nir_src_for_ssa(&load->dest.ssa);
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store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
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store->src[2] = nir_src_for_ssa(offset);
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nir_intrinsic_set_write_mask(store, 0xf);
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store->num_components = 4;
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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VkResult radv_device_init_meta_buffer_state(struct radv_device *device)
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{
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VkResult result;
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struct radv_shader_module fill_cs = { .nir = NULL };
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struct radv_shader_module copy_cs = { .nir = NULL };
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zero(device->meta_state.buffer);
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fill_cs.nir = build_buffer_fill_shader(device);
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copy_cs.nir = build_buffer_copy_shader(device);
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VkDescriptorSetLayoutCreateInfo fill_ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.bindingCount = 1,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&fill_ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.buffer.fill_ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkDescriptorSetLayoutCreateInfo copy_ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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©_ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.buffer.copy_ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo fill_pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.buffer.fill_ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 4},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&fill_pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.buffer.fill_p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo copy_pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.buffer.copy_ds_layout,
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.pushConstantRangeCount = 0,
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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©_pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.buffer.copy_p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineShaderStageCreateInfo fill_pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&fill_cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo fill_vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = fill_pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.buffer.fill_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &fill_vk_pipeline_info, NULL,
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&device->meta_state.buffer.fill_pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineShaderStageCreateInfo copy_pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(©_cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo copy_vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = copy_pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.buffer.copy_p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, ©_vk_pipeline_info, NULL,
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&device->meta_state.buffer.copy_pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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ralloc_free(fill_cs.nir);
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ralloc_free(copy_cs.nir);
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return VK_SUCCESS;
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fail:
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radv_device_finish_meta_buffer_state(device);
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ralloc_free(fill_cs.nir);
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ralloc_free(copy_cs.nir);
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return result;
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}
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void radv_device_finish_meta_buffer_state(struct radv_device *device)
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{
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if (device->meta_state.buffer.copy_pipeline)
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radv_DestroyPipeline(radv_device_to_handle(device),
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device->meta_state.buffer.copy_pipeline,
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&device->meta_state.alloc);
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if (device->meta_state.buffer.fill_pipeline)
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radv_DestroyPipeline(radv_device_to_handle(device),
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device->meta_state.buffer.fill_pipeline,
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&device->meta_state.alloc);
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if (device->meta_state.buffer.copy_p_layout)
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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device->meta_state.buffer.copy_p_layout,
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&device->meta_state.alloc);
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if (device->meta_state.buffer.fill_p_layout)
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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device->meta_state.buffer.fill_p_layout,
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&device->meta_state.alloc);
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if (device->meta_state.buffer.copy_ds_layout)
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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device->meta_state.buffer.copy_ds_layout,
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&device->meta_state.alloc);
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if (device->meta_state.buffer.fill_ds_layout)
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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device->meta_state.buffer.fill_ds_layout,
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&device->meta_state.alloc);
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}
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static void fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
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struct radeon_winsys_bo *bo,
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uint64_t offset, uint64_t size, uint32_t value)
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{
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struct radv_device *device = cmd_buffer->device;
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uint64_t block_count = round_up_u64(size, 1024);
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struct radv_meta_saved_compute_state saved_state;
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VkDescriptorSet ds;
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radv_meta_save_compute(&saved_state, cmd_buffer, 4);
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radv_temp_descriptor_set_create(device, cmd_buffer,
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device->meta_state.buffer.fill_ds_layout,
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&ds);
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struct radv_buffer dst_buffer = {
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.bo = bo,
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.offset = offset,
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.size = size
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};
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radv_UpdateDescriptorSets(radv_device_to_handle(device),
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1, /* writeCount */
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(VkWriteDescriptorSet[]) {
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = ds,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &(VkDescriptorBufferInfo) {
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.buffer = radv_buffer_to_handle(&dst_buffer),
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.offset = 0,
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.range = size
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}
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}
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}, 0, NULL);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.buffer.fill_pipeline);
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radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.buffer.fill_p_layout, 0, 1,
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&ds, 0, NULL);
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radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
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device->meta_state.buffer.fill_p_layout,
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VK_SHADER_STAGE_COMPUTE_BIT, 0, 4,
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&value);
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radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
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radv_temp_descriptor_set_destroy(device, ds);
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radv_meta_restore_compute(&saved_state, cmd_buffer, 4);
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}
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static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
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struct radeon_winsys_bo *src_bo,
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struct radeon_winsys_bo *dst_bo,
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uint64_t src_offset, uint64_t dst_offset,
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uint64_t size)
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{
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struct radv_device *device = cmd_buffer->device;
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uint64_t block_count = round_up_u64(size, 1024);
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struct radv_meta_saved_compute_state saved_state;
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VkDescriptorSet ds;
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radv_meta_save_compute(&saved_state, cmd_buffer, 0);
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radv_temp_descriptor_set_create(device, cmd_buffer,
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device->meta_state.buffer.copy_ds_layout,
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&ds);
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struct radv_buffer dst_buffer = {
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.bo = dst_bo,
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.offset = dst_offset,
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.size = size
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};
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struct radv_buffer src_buffer = {
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.bo = src_bo,
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.offset = src_offset,
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.size = size
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};
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radv_UpdateDescriptorSets(radv_device_to_handle(device),
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2, /* writeCount */
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(VkWriteDescriptorSet[]) {
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = ds,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &(VkDescriptorBufferInfo) {
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.buffer = radv_buffer_to_handle(&dst_buffer),
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.offset = 0,
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.range = size
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}
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},
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstSet = ds,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &(VkDescriptorBufferInfo) {
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.buffer = radv_buffer_to_handle(&src_buffer),
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.offset = 0,
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.range = size
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}
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}
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}, 0, NULL);
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.buffer.copy_pipeline);
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radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer),
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.buffer.copy_p_layout, 0, 1,
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&ds, 0, NULL);
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radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
|
|
|
|
radv_temp_descriptor_set_destroy(device, ds);
|
|
|
|
radv_meta_restore_compute(&saved_state, cmd_buffer, 0);
|
|
}
|
|
|
|
|
|
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radeon_winsys_bo *bo,
|
|
uint64_t offset, uint64_t size, uint32_t value)
|
|
{
|
|
assert(!(offset & 3));
|
|
assert(!(size & 3));
|
|
|
|
if (size >= 4096)
|
|
fill_buffer_shader(cmd_buffer, bo, offset, size, value);
|
|
else if (size) {
|
|
uint64_t va = cmd_buffer->device->ws->buffer_get_va(bo);
|
|
va += offset;
|
|
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
|
|
si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
|
|
}
|
|
}
|
|
|
|
static
|
|
void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
|
|
struct radeon_winsys_bo *src_bo,
|
|
struct radeon_winsys_bo *dst_bo,
|
|
uint64_t src_offset, uint64_t dst_offset,
|
|
uint64_t size)
|
|
{
|
|
if (size >= 4096 && !(size & 3) && !(src_offset & 3) && !(dst_offset & 3))
|
|
copy_buffer_shader(cmd_buffer, src_bo, dst_bo,
|
|
src_offset, dst_offset, size);
|
|
else if (size) {
|
|
uint64_t src_va = cmd_buffer->device->ws->buffer_get_va(src_bo);
|
|
uint64_t dst_va = cmd_buffer->device->ws->buffer_get_va(dst_bo);
|
|
src_va += src_offset;
|
|
dst_va += dst_offset;
|
|
|
|
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, src_bo, 8);
|
|
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_bo, 8);
|
|
|
|
si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
|
|
}
|
|
}
|
|
|
|
void radv_CmdFillBuffer(
|
|
VkCommandBuffer commandBuffer,
|
|
VkBuffer dstBuffer,
|
|
VkDeviceSize dstOffset,
|
|
VkDeviceSize fillSize,
|
|
uint32_t data)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
|
|
|
|
if (fillSize == VK_WHOLE_SIZE)
|
|
fillSize = (dst_buffer->size - dstOffset) & ~3ull;
|
|
|
|
radv_fill_buffer(cmd_buffer, dst_buffer->bo, dst_buffer->offset + dstOffset,
|
|
fillSize, data);
|
|
}
|
|
|
|
void radv_CmdCopyBuffer(
|
|
VkCommandBuffer commandBuffer,
|
|
VkBuffer srcBuffer,
|
|
VkBuffer destBuffer,
|
|
uint32_t regionCount,
|
|
const VkBufferCopy* pRegions)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
RADV_FROM_HANDLE(radv_buffer, src_buffer, srcBuffer);
|
|
RADV_FROM_HANDLE(radv_buffer, dest_buffer, destBuffer);
|
|
|
|
for (unsigned r = 0; r < regionCount; r++) {
|
|
uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
|
|
uint64_t dest_offset = dest_buffer->offset + pRegions[r].dstOffset;
|
|
uint64_t copy_size = pRegions[r].size;
|
|
|
|
radv_copy_buffer(cmd_buffer, src_buffer->bo, dest_buffer->bo,
|
|
src_offset, dest_offset, copy_size);
|
|
}
|
|
}
|
|
|
|
void radv_CmdUpdateBuffer(
|
|
VkCommandBuffer commandBuffer,
|
|
VkBuffer dstBuffer,
|
|
VkDeviceSize dstOffset,
|
|
VkDeviceSize dataSize,
|
|
const void* pData)
|
|
{
|
|
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
|
|
RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
|
|
uint64_t words = dataSize / 4;
|
|
uint64_t va = cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
|
|
va += dstOffset + dst_buffer->offset;
|
|
|
|
assert(!(dataSize & 3));
|
|
assert(!(va & 3));
|
|
|
|
if (dataSize < 4096) {
|
|
cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, dst_buffer->bo, 8);
|
|
|
|
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
|
|
|
|
radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0));
|
|
radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
|
|
S_370_WR_CONFIRM(1) |
|
|
S_370_ENGINE_SEL(V_370_ME));
|
|
radeon_emit(cmd_buffer->cs, va);
|
|
radeon_emit(cmd_buffer->cs, va >> 32);
|
|
radeon_emit_array(cmd_buffer->cs, pData, words);
|
|
} else {
|
|
uint32_t buf_offset;
|
|
radv_cmd_buffer_upload_data(cmd_buffer, dataSize, 32, pData, &buf_offset);
|
|
radv_copy_buffer(cmd_buffer, cmd_buffer->upload.upload_bo, dst_buffer->bo,
|
|
buf_offset, dstOffset + dst_buffer->offset, dataSize);
|
|
}
|
|
}
|