mirror of https://gitlab.freedesktop.org/mesa/mesa
117 lines
4.5 KiB
C
117 lines
4.5 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_PIPELINE_H
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#define RADV_PIPELINE_H
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#include "util/mesa-sha1.h"
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#include "nir.h"
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#include "vk_pipeline.h"
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#include "vk_pipeline_cache.h"
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#include "radv_radeon_winsys.h"
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struct radv_device;
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struct radv_shader_stage_key;
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struct radv_shader_stage;
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struct radv_pipeline_layout;
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struct radv_graphics_state_key;
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struct radv_shader_layout;
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enum radv_pipeline_type {
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RADV_PIPELINE_GRAPHICS,
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RADV_PIPELINE_GRAPHICS_LIB,
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/* Compute pipeline */
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RADV_PIPELINE_COMPUTE,
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/* Raytracing pipeline */
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RADV_PIPELINE_RAY_TRACING,
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RADV_PIPELINE_TYPE_COUNT,
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};
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struct radv_pipeline {
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struct vk_object_base base;
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uint8_t sha1[SHA1_DIGEST_LENGTH];
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enum radv_pipeline_type type;
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VkPipelineCreateFlags2KHR create_flags;
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struct vk_pipeline_cache_object *cache_object;
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bool is_internal;
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bool need_indirect_descriptor_sets;
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struct radv_shader *shaders[MESA_VULKAN_SHADER_STAGES];
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struct radv_shader *gs_copy_shader;
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struct radeon_cmdbuf cs;
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uint32_t ctx_cs_hash;
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struct radeon_cmdbuf ctx_cs;
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uint32_t user_data_0[MESA_VULKAN_SHADER_STAGES];
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/* Unique pipeline hash identifier. */
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uint64_t pipeline_hash;
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/* Pipeline layout info. */
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uint32_t push_constant_size;
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uint32_t dynamic_offset_count;
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};
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VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, base, VkPipeline, VK_OBJECT_TYPE_PIPELINE)
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#define RADV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
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static inline struct radv_##pipe_type##_pipeline *radv_pipeline_to_##pipe_type(struct radv_pipeline *pipeline) \
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{ \
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assert(pipeline->type == pipe_enum); \
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return (struct radv_##pipe_type##_pipeline *)pipeline; \
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}
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bool radv_pipeline_capture_shaders(const struct radv_device *device, VkPipelineCreateFlags2KHR flags);
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bool radv_shader_need_indirect_descriptor_sets(const struct radv_shader *shader);
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bool radv_pipeline_capture_shader_stats(const struct radv_device *device, VkPipelineCreateFlags2KHR flags);
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void radv_pipeline_init(struct radv_device *device, struct radv_pipeline *pipeline, enum radv_pipeline_type type);
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void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline,
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const VkAllocationCallbacks *allocator);
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struct radv_shader_stage_key radv_pipeline_get_shader_key(const struct radv_device *device,
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const VkPipelineShaderStageCreateInfo *stage,
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VkPipelineCreateFlags2KHR flags, const void *pNext);
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void radv_pipeline_stage_init(const VkPipelineShaderStageCreateInfo *sinfo, const struct radv_pipeline_layout *layout,
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const struct radv_shader_stage_key *stage_key, struct radv_shader_stage *out_stage);
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void radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, gl_shader_stage stage,
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struct radv_shader_layout *layout);
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bool radv_mem_vectorize_callback(unsigned align_mul, unsigned align_offset, unsigned bit_size, unsigned num_components,
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nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data);
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void radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
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struct radv_shader_stage *stage);
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bool radv_shader_should_clear_lds(const struct radv_device *device, const nir_shader *shader);
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VkPipelineShaderStageCreateInfo *radv_copy_shader_stage_create_info(struct radv_device *device, uint32_t stageCount,
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const VkPipelineShaderStageCreateInfo *pStages,
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void *mem_ctx);
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void radv_pipeline_hash(const struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
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struct mesa_sha1 *ctx);
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void radv_pipeline_hash_shader_stage(const VkPipelineShaderStageCreateInfo *sinfo,
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const struct radv_shader_stage_key *stage_key, struct mesa_sha1 *ctx);
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#endif /* RADV_PIPELINE_H */
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