mirror of https://gitlab.freedesktop.org/mesa/mesa
382 lines
12 KiB
C
382 lines
12 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_IMAGE_H
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#define RADV_IMAGE_H
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#include "ac_surface.h"
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#include "radv_device.h"
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#include "radv_physical_device.h"
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#include "radv_radeon_winsys.h"
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#include "vk_format.h"
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#include "vk_image.h"
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static const VkImageUsageFlags RADV_IMAGE_USAGE_WRITE_BITS =
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VK_IMAGE_USAGE_TRANSFER_DST_BIT | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT |
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VK_IMAGE_USAGE_STORAGE_BIT;
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struct radv_image_plane {
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VkFormat format;
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struct radeon_surf surface;
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};
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struct radv_image_binding {
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/* Set when bound */
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struct radeon_winsys_bo *bo;
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VkDeviceSize offset;
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uint64_t bo_va;
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uint64_t range;
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};
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struct radv_image {
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struct vk_image vk;
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VkDeviceSize size;
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uint32_t alignment;
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unsigned queue_family_mask;
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bool exclusive;
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bool shareable;
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bool l2_coherent;
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bool dcc_sign_reinterpret;
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bool support_comp_to_single;
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struct radv_image_binding bindings[3];
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bool tc_compatible_cmask;
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uint64_t clear_value_offset;
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uint64_t fce_pred_offset;
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uint64_t dcc_pred_offset;
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/*
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* Metadata for the TC-compat zrange workaround. If the 32-bit value
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* stored at this offset is UINT_MAX, the driver will emit
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* DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
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* SET_CONTEXT_REG packet.
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*/
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uint64_t tc_compat_zrange_offset;
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/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
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VkDeviceMemory owned_memory;
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unsigned plane_count;
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bool disjoint;
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struct radv_image_plane planes[0];
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};
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VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
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static inline bool
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radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent)
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{
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if (extent->width != image->vk.extent.width || extent->height != image->vk.extent.height ||
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extent->depth != image->vk.extent.depth)
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return false;
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return true;
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}
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/**
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* Return whether the image has CMASK metadata for color surfaces.
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*/
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static inline bool
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radv_image_has_cmask(const struct radv_image *image)
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{
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return image->planes[0].surface.cmask_offset;
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}
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/**
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* Return whether the image has FMASK metadata for color surfaces.
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*/
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static inline bool
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radv_image_has_fmask(const struct radv_image *image)
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{
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return image->planes[0].surface.fmask_offset;
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}
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/**
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* Return whether the image has DCC metadata for color surfaces.
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*/
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static inline bool
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radv_image_has_dcc(const struct radv_image *image)
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{
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return !(image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER) && image->planes[0].surface.meta_offset;
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}
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/**
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* Return whether the image is TC-compatible CMASK.
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*/
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static inline bool
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radv_image_is_tc_compat_cmask(const struct radv_image *image)
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{
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return radv_image_has_fmask(image) && image->tc_compatible_cmask;
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}
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/**
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* Return whether DCC metadata is enabled for a level.
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*/
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static inline bool
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radv_dcc_enabled(const struct radv_image *image, unsigned level)
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{
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return radv_image_has_dcc(image) && level < image->planes[0].surface.num_meta_levels;
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}
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/**
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* Return whether the image has CB metadata.
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*/
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static inline bool
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radv_image_has_CB_metadata(const struct radv_image *image)
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{
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return radv_image_has_cmask(image) || radv_image_has_fmask(image) || radv_image_has_dcc(image);
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}
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/**
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* Return whether the image has HTILE metadata for depth surfaces.
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*/
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static inline bool
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radv_image_has_htile(const struct radv_image *image)
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{
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return image->planes[0].surface.flags & RADEON_SURF_Z_OR_SBUFFER && image->planes[0].surface.meta_size;
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}
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/**
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* Return whether the image has VRS HTILE metadata for depth surfaces
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*/
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static inline bool
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radv_image_has_vrs_htile(const struct radv_device *device, const struct radv_image *image)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const enum amd_gfx_level gfx_level = pdev->info.gfx_level;
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/* Any depth buffer can potentially use VRS on GFX10.3. */
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return gfx_level == GFX10_3 && device->vk.enabled_features.attachmentFragmentShadingRate &&
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radv_image_has_htile(image) && (image->vk.usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
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}
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/**
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* Return whether HTILE metadata is enabled for a level.
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*/
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static inline bool
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radv_htile_enabled(const struct radv_image *image, unsigned level)
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{
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return radv_image_has_htile(image) && level < image->planes[0].surface.num_meta_levels;
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}
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/**
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* Return whether the image is TC-compatible HTILE.
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*/
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static inline bool
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radv_image_is_tc_compat_htile(const struct radv_image *image)
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{
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return radv_image_has_htile(image) && (image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE);
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}
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/**
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* Return whether the entire HTILE buffer can be used for depth in order to
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* improve HiZ Z-Range precision.
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*/
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static inline bool
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radv_image_tile_stencil_disabled(const struct radv_device *device, const struct radv_image *image)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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if (pdev->info.gfx_level >= GFX9) {
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return !vk_format_has_stencil(image->vk.format) && !radv_image_has_vrs_htile(device, image);
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} else {
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/* Due to a hw bug, TILE_STENCIL_DISABLE must be set to 0 for
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* the TC-compat ZRANGE issue even if no stencil is used.
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*/
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return !vk_format_has_stencil(image->vk.format) && !radv_image_is_tc_compat_htile(image);
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}
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}
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static inline bool
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radv_image_has_clear_value(const struct radv_image *image)
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{
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return image->clear_value_offset != 0;
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}
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static inline uint64_t
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radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level)
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{
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assert(radv_image_has_clear_value(image));
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uint64_t va = radv_buffer_get_va(image->bindings[0].bo);
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va += image->bindings[0].offset + image->clear_value_offset + base_level * 8;
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return va;
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}
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static inline uint64_t
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radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level)
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{
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assert(image->fce_pred_offset != 0);
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uint64_t va = radv_buffer_get_va(image->bindings[0].bo);
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va += image->bindings[0].offset + image->fce_pred_offset + base_level * 8;
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return va;
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}
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static inline uint64_t
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radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level)
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{
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assert(image->dcc_pred_offset != 0);
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uint64_t va = radv_buffer_get_va(image->bindings[0].bo);
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va += image->bindings[0].offset + image->dcc_pred_offset + base_level * 8;
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return va;
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}
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static inline uint64_t
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radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level)
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{
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assert(image->tc_compat_zrange_offset != 0);
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uint64_t va = radv_buffer_get_va(image->bindings[0].bo);
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va += image->bindings[0].offset + image->tc_compat_zrange_offset + base_level * 4;
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return va;
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}
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static inline uint64_t
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radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level)
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{
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assert(radv_image_has_clear_value(image));
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uint64_t va = radv_buffer_get_va(image->bindings[0].bo);
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va += image->bindings[0].offset + image->clear_value_offset + base_level * 8;
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return va;
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}
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static inline uint32_t
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radv_get_htile_initial_value(const struct radv_device *device, const struct radv_image *image)
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{
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uint32_t initial_value;
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if (radv_image_tile_stencil_disabled(device, image)) {
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/* Z only (no stencil):
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*
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* |31 18|17 4|3 0|
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* +---------+---------+-------+
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* | Max Z | Min Z | ZMask |
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*/
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initial_value = 0xfffc000f;
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} else {
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/* Z and stencil:
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*
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* |31 12|11 10|9 8|7 6|5 4|3 0|
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* +-----------+-----+------+-----+-----+-------+
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* | Z Range | | SMem | SR1 | SR0 | ZMask |
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*
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* SR0/SR1 contains the stencil test results. Initializing
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* SR0/SR1 to 0x3 means the stencil test result is unknown.
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*
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* Z, stencil and 4 bit VRS encoding:
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* |31 12|11 10|9 8|7 6|5 4|3 0|
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* +-----------+------------+------+------------+-----+-------+
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* | Z Range | VRS y-rate | SMem | VRS x-rate | SR0 | ZMask |
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*/
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if (radv_image_has_vrs_htile(device, image)) {
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/* Initialize the VRS x-rate value at 0, so the hw interprets it as 1 sample. */
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initial_value = 0xfffff33f;
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} else {
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initial_value = 0xfffff3ff;
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}
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}
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return initial_value;
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}
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static inline bool
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radv_image_get_iterate256(const struct radv_device *device, struct radv_image *image)
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{
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const struct radv_physical_device *pdev = radv_device_physical(device);
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/* ITERATE_256 is required for depth or stencil MSAA images that are TC-compatible HTILE. */
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return pdev->info.gfx_level >= GFX10 &&
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(image->vk.usage & (VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT | VK_IMAGE_USAGE_TRANSFER_DST_BIT)) &&
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radv_image_is_tc_compat_htile(image) && image->vk.samples > 1;
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}
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bool radv_are_formats_dcc_compatible(const struct radv_physical_device *pdev, const void *pNext, VkFormat format,
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VkImageCreateFlags flags, bool *sign_reinterpret);
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bool radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image);
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bool radv_image_use_dcc_predication(const struct radv_device *device, const struct radv_image *image);
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unsigned radv_map_swizzle(unsigned swizzle);
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void radv_compose_swizzle(const struct util_format_description *desc, const VkComponentMapping *mapping,
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enum pipe_swizzle swizzle[4]);
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bool vi_alpha_is_on_msb(const struct radv_device *device, const VkFormat format);
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void radv_init_metadata(struct radv_device *device, struct radv_image *image, struct radeon_bo_metadata *metadata);
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void radv_image_override_offset_stride(struct radv_device *device, struct radv_image *image, uint64_t offset,
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uint32_t stride);
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bool radv_image_can_fast_clear(const struct radv_device *device, const struct radv_image *image);
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struct ac_surf_info radv_get_ac_surf_info(struct radv_device *device, const struct radv_image *image);
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struct radv_image_create_info {
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const VkImageCreateInfo *vk_info;
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bool scanout;
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bool no_metadata_planes;
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bool prime_blit_src;
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const struct radeon_bo_metadata *bo_metadata;
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};
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VkResult radv_image_create_layout(struct radv_device *device, struct radv_image_create_info create_info,
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const struct VkImageDrmFormatModifierExplicitCreateInfoEXT *mod_info,
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const struct VkVideoProfileListInfoKHR *profile_list, struct radv_image *image);
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VkResult radv_image_create(VkDevice _device, const struct radv_image_create_info *info,
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const VkAllocationCallbacks *alloc, VkImage *pImage, bool is_internal);
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unsigned radv_plane_from_aspect(VkImageAspectFlags mask);
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VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask);
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/* Whether the image has a htile that is known consistent with the contents of
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* the image and is allowed to be in compressed form.
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*
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* If this is false reads that don't use the htile should be able to return
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* correct results.
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*/
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bool radv_layout_is_htile_compressed(const struct radv_device *device, const struct radv_image *image,
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VkImageLayout layout, unsigned queue_mask);
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bool radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_image *image, unsigned level,
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VkImageLayout layout, unsigned queue_mask);
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bool radv_layout_dcc_compressed(const struct radv_device *device, const struct radv_image *image, unsigned level,
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VkImageLayout layout, unsigned queue_mask);
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enum radv_fmask_compression {
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RADV_FMASK_COMPRESSION_NONE,
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RADV_FMASK_COMPRESSION_PARTIAL,
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RADV_FMASK_COMPRESSION_FULL,
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};
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enum radv_fmask_compression radv_layout_fmask_compression(const struct radv_device *device,
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const struct radv_image *image, VkImageLayout layout,
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unsigned queue_mask);
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unsigned radv_image_queue_family_mask(const struct radv_image *image, enum radv_queue_family family,
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enum radv_queue_family queue_family);
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bool radv_image_is_renderable(const struct radv_device *device, const struct radv_image *image);
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unsigned radv_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil);
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#endif /* RADV_IMAGE_H */
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