mirror of https://gitlab.freedesktop.org/mesa/mesa
315 lines
11 KiB
C
315 lines
11 KiB
C
/**********************************************************
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* Copyright 2008-2009 VMware, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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**********************************************************/
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#include "pipe/p_defines.h"
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#include "util/u_bitmask.h"
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#include "util/u_inlines.h"
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#include "util/u_math.h"
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#include "util/u_memory.h"
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#include "svga_context.h"
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#include "svga_hw_reg.h"
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#include "svga_cmd.h"
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static inline unsigned
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svga_translate_compare_func(unsigned func)
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{
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switch (func) {
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case PIPE_FUNC_NEVER: return SVGA3D_CMP_NEVER;
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case PIPE_FUNC_LESS: return SVGA3D_CMP_LESS;
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case PIPE_FUNC_LEQUAL: return SVGA3D_CMP_LESSEQUAL;
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case PIPE_FUNC_GREATER: return SVGA3D_CMP_GREATER;
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case PIPE_FUNC_GEQUAL: return SVGA3D_CMP_GREATEREQUAL;
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case PIPE_FUNC_NOTEQUAL: return SVGA3D_CMP_NOTEQUAL;
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case PIPE_FUNC_EQUAL: return SVGA3D_CMP_EQUAL;
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case PIPE_FUNC_ALWAYS: return SVGA3D_CMP_ALWAYS;
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default:
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assert(0);
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return SVGA3D_CMP_ALWAYS;
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}
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}
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static inline unsigned
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svga_translate_stencil_op(unsigned op)
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{
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switch (op) {
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case PIPE_STENCIL_OP_KEEP: return SVGA3D_STENCILOP_KEEP;
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case PIPE_STENCIL_OP_ZERO: return SVGA3D_STENCILOP_ZERO;
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case PIPE_STENCIL_OP_REPLACE: return SVGA3D_STENCILOP_REPLACE;
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case PIPE_STENCIL_OP_INCR: return SVGA3D_STENCILOP_INCRSAT;
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case PIPE_STENCIL_OP_DECR: return SVGA3D_STENCILOP_DECRSAT;
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case PIPE_STENCIL_OP_INCR_WRAP: return SVGA3D_STENCILOP_INCR;
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case PIPE_STENCIL_OP_DECR_WRAP: return SVGA3D_STENCILOP_DECR;
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case PIPE_STENCIL_OP_INVERT: return SVGA3D_STENCILOP_INVERT;
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default:
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assert(0);
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return SVGA3D_STENCILOP_KEEP;
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}
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}
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/**
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* Define a vgpu10 depth/stencil state object for the given
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* svga depth/stencil state.
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*/
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static void
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define_depth_stencil_state_object(struct svga_context *svga,
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struct svga_depth_stencil_state *ds)
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{
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assert(svga_have_vgpu10(svga));
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ds->id = util_bitmask_add(svga->ds_object_id_bm);
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/* spot check that these comparision tokens are the same */
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STATIC_ASSERT(SVGA3D_COMPARISON_NEVER == SVGA3D_CMP_NEVER);
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STATIC_ASSERT(SVGA3D_COMPARISON_LESS == SVGA3D_CMP_LESS);
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STATIC_ASSERT(SVGA3D_COMPARISON_NOT_EQUAL == SVGA3D_CMP_NOTEQUAL);
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/* Note: we use the ds->stencil[0].enabled value for both the front
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* and back-face enables. If single-side stencil is used, we'll have
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* set the back state the same as the front state.
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*/
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SVGA_RETRY(svga, SVGA3D_vgpu10_DefineDepthStencilState
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(svga->swc,
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ds->id,
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/* depth/Z */
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ds->zenable,
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ds->zwriteenable,
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ds->zfunc,
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/* Stencil */
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ds->stencil[0].enabled, /*f|b*/
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ds->stencil[0].enabled, /*f*/
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ds->stencil[0].enabled, /*b*/
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ds->stencil_mask,
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ds->stencil_writemask,
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/* front stencil */
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ds->stencil[0].fail,
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ds->stencil[0].zfail,
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ds->stencil[0].pass,
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ds->stencil[0].func,
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/* back stencil */
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ds->stencil[1].fail,
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ds->stencil[1].zfail,
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ds->stencil[1].pass,
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ds->stencil[1].func));
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}
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static void *
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svga_create_depth_stencil_state(struct pipe_context *pipe,
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const struct pipe_depth_stencil_alpha_state *templ)
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{
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struct svga_context *svga = svga_context(pipe);
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struct svga_depth_stencil_state *ds = CALLOC_STRUCT(svga_depth_stencil_state);
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if (!ds)
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return NULL;
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/* Don't try to figure out CW/CCW correspondence with
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* stencil[0]/[1] at this point. Presumably this can change as
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* back/front face are modified.
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*/
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ds->stencil[0].enabled = templ->stencil[0].enabled;
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if (ds->stencil[0].enabled) {
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ds->stencil[0].func = svga_translate_compare_func(templ->stencil[0].func);
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ds->stencil[0].fail = svga_translate_stencil_op(templ->stencil[0].fail_op);
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ds->stencil[0].zfail = svga_translate_stencil_op(templ->stencil[0].zfail_op);
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ds->stencil[0].pass = svga_translate_stencil_op(templ->stencil[0].zpass_op);
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/* SVGA3D has one ref/mask/writemask triple shared between front &
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* back face stencil. We really need two:
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*/
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ds->stencil_mask = templ->stencil[0].valuemask & 0xff;
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ds->stencil_writemask = templ->stencil[0].writemask & 0xff;
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}
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else {
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ds->stencil[0].func = SVGA3D_CMP_ALWAYS;
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ds->stencil[0].fail = SVGA3D_STENCILOP_KEEP;
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ds->stencil[0].zfail = SVGA3D_STENCILOP_KEEP;
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ds->stencil[0].pass = SVGA3D_STENCILOP_KEEP;
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}
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ds->stencil[1].enabled = templ->stencil[1].enabled;
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if (templ->stencil[1].enabled) {
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assert(templ->stencil[0].enabled);
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/* two-sided stencil */
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ds->stencil[1].func = svga_translate_compare_func(templ->stencil[1].func);
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ds->stencil[1].fail = svga_translate_stencil_op(templ->stencil[1].fail_op);
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ds->stencil[1].zfail = svga_translate_stencil_op(templ->stencil[1].zfail_op);
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ds->stencil[1].pass = svga_translate_stencil_op(templ->stencil[1].zpass_op);
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ds->stencil_mask = templ->stencil[1].valuemask & 0xff;
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ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
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if (templ->stencil[1].valuemask != templ->stencil[0].valuemask) {
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util_debug_message(&svga->debug.callback, CONFORMANCE,
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"two-sided stencil mask not supported "
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"(front=0x%x, back=0x%x)",
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templ->stencil[0].valuemask,
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templ->stencil[1].valuemask);
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}
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if (templ->stencil[1].writemask != templ->stencil[0].writemask) {
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util_debug_message(&svga->debug.callback, CONFORMANCE,
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"two-sided stencil writemask not supported "
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"(front=0x%x, back=0x%x)",
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templ->stencil[0].writemask,
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templ->stencil[1].writemask);
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}
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}
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else {
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/* back face state is same as front-face state */
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ds->stencil[1].func = ds->stencil[0].func;
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ds->stencil[1].fail = ds->stencil[0].fail;
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ds->stencil[1].zfail = ds->stencil[0].zfail;
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ds->stencil[1].pass = ds->stencil[0].pass;
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}
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ds->zenable = templ->depth_enabled;
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if (ds->zenable) {
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ds->zfunc = svga_translate_compare_func(templ->depth_func);
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ds->zwriteenable = templ->depth_writemask;
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}
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else {
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ds->zfunc = SVGA3D_CMP_ALWAYS;
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}
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ds->alphatestenable = templ->alpha_enabled;
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if (ds->alphatestenable) {
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ds->alphafunc = svga_translate_compare_func(templ->alpha_func);
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ds->alpharef = templ->alpha_ref_value;
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}
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else {
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ds->alphafunc = SVGA3D_CMP_ALWAYS;
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}
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if (svga_have_vgpu10(svga)) {
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define_depth_stencil_state_object(svga, ds);
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}
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svga->hud.num_depthstencil_objects++;
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SVGA_STATS_COUNT_INC(svga_screen(svga->pipe.screen)->sws,
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SVGA_STATS_COUNT_DEPTHSTENCILSTATE);
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return ds;
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}
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static void
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svga_bind_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)
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{
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struct svga_context *svga = svga_context(pipe);
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if (svga_have_vgpu10(svga)) {
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/* flush any previously queued drawing before changing state */
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svga_hwtnl_flush_retry(svga);
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}
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svga->curr.depth = (const struct svga_depth_stencil_state *)depth_stencil;
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svga->dirty |= SVGA_NEW_DEPTH_STENCIL_ALPHA;
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}
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static void
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svga_delete_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)
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{
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struct svga_context *svga = svga_context(pipe);
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struct svga_depth_stencil_state *ds =
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(struct svga_depth_stencil_state *) depth_stencil;
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if (svga_have_vgpu10(svga)) {
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svga_hwtnl_flush_retry(svga);
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assert(ds->id != SVGA3D_INVALID_ID);
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SVGA_RETRY(svga, SVGA3D_vgpu10_DestroyDepthStencilState(svga->swc,
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ds->id));
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if (ds->id == svga->state.hw_draw.depth_stencil_id)
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svga->state.hw_draw.depth_stencil_id = SVGA3D_INVALID_ID;
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util_bitmask_clear(svga->ds_object_id_bm, ds->id);
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ds->id = SVGA3D_INVALID_ID;
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}
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FREE(depth_stencil);
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svga->hud.num_depthstencil_objects--;
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}
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static void
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svga_set_stencil_ref(struct pipe_context *pipe,
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const struct pipe_stencil_ref stencil_ref)
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{
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struct svga_context *svga = svga_context(pipe);
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if (svga_have_vgpu10(svga)) {
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/* flush any previously queued drawing before changing state */
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svga_hwtnl_flush_retry(svga);
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}
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svga->curr.stencil_ref = stencil_ref;
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svga->dirty |= SVGA_NEW_STENCIL_REF;
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}
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static void
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svga_set_sample_mask(struct pipe_context *pipe,
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unsigned sample_mask)
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{
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struct svga_context *svga = svga_context(pipe);
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svga->curr.sample_mask = sample_mask;
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svga->dirty |= SVGA_NEW_BLEND; /* See emit_rss_vgpu10() */
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}
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static void
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svga_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
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{
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/* This specifies the minimum number of times the fragment shader
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* must run when doing per-sample shading for a MSAA render target.
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* For our SVGA3D device, the FS is automatically run in per-sample
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* mode if it uses the sample ID or sample position registers.
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*/
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}
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void
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svga_init_depth_stencil_functions(struct svga_context *svga)
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{
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svga->pipe.create_depth_stencil_alpha_state = svga_create_depth_stencil_state;
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svga->pipe.bind_depth_stencil_alpha_state = svga_bind_depth_stencil_state;
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svga->pipe.delete_depth_stencil_alpha_state = svga_delete_depth_stencil_state;
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svga->pipe.set_stencil_ref = svga_set_stencil_ref;
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svga->pipe.set_sample_mask = svga_set_sample_mask;
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svga->pipe.set_min_samples = svga_set_min_samples;
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}
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