mirror of https://gitlab.freedesktop.org/mesa/mesa
209 lines
6.8 KiB
C
209 lines
6.8 KiB
C
/*
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* Copyright (c) 2017 Rob Clark <robdclark@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _AFUC_H_
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#define _AFUC_H_
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#include <stdbool.h>
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#include "util/macros.h"
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/*
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TODO kernel debugfs to inject packet into rb for easier experimentation. It
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should trigger reloading pfp/me and resetting gpu..
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Actually maybe it should be flag on submit ioctl to be able to deal w/ relocs,
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should be restricted to CAP_ADMIN and probably compile option too (default=n).
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if flag set, copy cmdstream bo contents into RB instead of IB'ing to it from
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RB.
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*/
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typedef enum {
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OPC_NOP,
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#define ALU(name) \
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OPC_##name, \
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OPC_##name##I,
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ALU(ADD) /* add immediate */
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ALU(ADDHI) /* add immediate (hi 32b of 64b) */
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ALU(SUB) /* subtract immediate */
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ALU(SUBHI) /* subtract immediate (hi 32b of 64b) */
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ALU(AND) /* AND immediate */
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ALU(OR) /* OR immediate */
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ALU(XOR) /* XOR immediate */
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ALU(NOT) /* bitwise not of immed (src1 ignored) */
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ALU(SHL) /* shift-left immediate */
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ALU(USHR) /* unsigned shift right by immediate */
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ALU(ISHR) /* signed shift right by immediate */
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ALU(ROT) /* rotate left (left shift with wrap-around) */
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ALU(MUL8) /* 8bit multiply by immediate */
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ALU(MIN)
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ALU(MAX)
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ALU(CMP) /* compare src to immed */
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ALU(BIC) /* AND with second source negated */
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OPC_SETBIT, /* Set or clear a bit dynamically */
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OPC_MOVI, /* move immediate */
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OPC_SETBITI, /* Set a bit */
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OPC_CLRBIT, /* Clear a bit */
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OPC_UBFX, /* Unsigned BitField eXtract */
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OPC_BFI, /* BitField Insert */
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#undef ALU
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/* Return the most-significant bit of src2, or 0 if src2 == 0 (the
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* same as if src2 == 1). src1 is ignored. Note that this overlaps
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* with STORE, so it can only be used with the two-source encoding.
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*/
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OPC_MSB,
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/* These seem something to do with setting some external state..
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* doesn't seem to map *directly* to registers, but I guess that
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* is where things end up. For example, this sequence in the
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* CP_INDIRECT_BUFFER handler:
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*
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* mov $02, $data ; low 32b of IB target address
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* mov $03, $data ; high 32b of IB target
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* mov $04, $data ; IB size in dwords
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* breq $04, 0x0, #l23 (#69, 04a2)
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* and $05, $18, 0x0003
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* shl $05, $05, 0x0002
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* cwrite $02, [$05 + 0x0b0], 0x8
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* cwrite $03, [$05 + 0x0b1], 0x8
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* cwrite $04, [$05 + 0x0b2], 0x8
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*
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* Note that CP_IB1/2_BASE_LO/HI/BUFSZ in 0x0b1f->0xb21 (IB1) and
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* 0x0b22->0x0b24 (IB2). Presumably $05 ends up w/ different value
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* for RB->IB1 vs IB1->IB2.
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*/
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OPC_CWRITE,
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OPC_CREAD,
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/* A6xx added new opcodes that let you read/write directly to memory (and
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* bypass the IOMMU?).
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*/
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OPC_STORE,
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OPC_LOAD,
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/* A6xx added new opcodes that let you read/write the state of the
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* SQE processor itself, like the call stack. This is mostly used by
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* preemption but is also used to set the preempt routine entrypoint.
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*/
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OPC_SREAD,
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OPC_SWRITE,
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OPC_BRNEI, /* relative branch (if $src != immed) */
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OPC_BREQI, /* relative branch (if $src == immed) */
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OPC_BRNEB, /* relative branch (if bit not set) */
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OPC_BREQB, /* relative branch (if bit is set) */
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OPC_RET, /* return */
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OPC_IRET, /* return from preemption interrupt handler */
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OPC_CALL, /* "function" call */
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OPC_WAITIN, /* wait for input (ie. wait for WPTR to advance) */
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OPC_BL, /* Branch and Link (same as the MIPS/ARM instruction) */
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OPC_SETSECURE, /* switch secure mode on/off */
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OPC_JUMPR, /* indirect jump with a register offset */
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OPC_SRET, /* Return instruction to use with "bl" */
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OPC_JUMPA, /* Absolute jump instruction */
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/* pseudo-opcodes without an actual encoding */
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OPC_BREQ,
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OPC_BRNE,
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OPC_JUMP,
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OPC_RAW_LITERAL,
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OPC_JUMPTBL,
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} afuc_opc;
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/**
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* Special GPR registers:
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*
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* Notes: (applicable to a6xx, double check a5xx)
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*
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* 0x1a:
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* $sp
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* 0x1b:
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* $lr: written by bl
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* 0x1d:
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* $addr: writes configure GPU reg address to read/write
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* (does not respect CP_PROTECT)
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* $memdata: reads from FIFO filled based on MEM_READ_DWORDS/
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* MEM_READ_ADDR
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* 0x1e: (note different mnemonic for src vs dst)
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* $usraddr: writes configure GPU reg address to read/write,
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* respecting CP_PROTECT
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* $regdata: reads from FIFO filled based on REG_READ_DWORDS/
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* REG_READ_ADDR
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* 0x1f:
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* $data: reads from from pm4 input stream
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* $data: writes to stream configured by write to $addr
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* or $usraddr
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*/
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typedef enum {
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REG_SP = 0x1a,
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REG_LR = 0x1b,
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REG_REM = 0x1c,
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REG_MEMDATA = 0x1d, /* when used as src */
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REG_ADDR = 0x1d, /* when used as dst */
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REG_REGDATA = 0x1e, /* when used as src */
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REG_USRADDR = 0x1e, /* when used as dst */
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REG_DATA = 0x1f,
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} afuc_reg;
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struct afuc_instr {
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afuc_opc opc;
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uint8_t dst;
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uint8_t src1;
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uint8_t src2;
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uint32_t immed;
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uint8_t shift;
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uint8_t bit;
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uint8_t xmov;
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uint8_t sds;
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uint32_t literal;
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int offset;
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const char *label;
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bool has_immed : 1;
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bool has_shift : 1;
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bool has_bit : 1;
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bool is_literal : 1;
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bool rep : 1;
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bool preincrement : 1;
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bool peek : 1;
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};
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/* Literal offsets are sometimes encoded as NOP instructions, which on a6xx+
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* must have a high 8 bits of 0x01.
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*/
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static inline uint32_t
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afuc_nop_literal(uint32_t x, unsigned gpuver)
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{
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assert((x >> 24) == 0);
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return gpuver < 6 ? x : x | (1 << 24);
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}
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void print_control_reg(uint32_t id);
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void print_sqe_reg(uint32_t id);
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void print_pipe_reg(uint32_t id);
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#endif /* _AFUC_H_ */
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