Samuel Pitoiset ad83c06a5f radv: fix missing cache flushes when clearing HTILE levels on GFX10+ ... The driver should accumulate the cache flush bits because if it uses CP DMA for clearing the last level, it won't flush. Found by inspection. Cc: 21.2 mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12170>		2021-08-03 12:59:57 +00:00
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addrlib	amd/addrlib: expose CMASK address equations to drivers on GFX9	2021-08-03 07:02:48 +00:00
ci	ci: update to VK-GL-CTS 1.2.7.0	2021-07-30 20:02:13 +00:00
common	ac/surface: implement CmaskAddrFromCoord in NIR	2021-08-03 07:02:48 +00:00
compiler	nir, aco: Remove vertex and primitive count overwrite intrinsic.	2021-08-02 11:38:25 +00:00
llvm	ac/llvm: implement v2f16 fsat	2021-08-02 10:02:51 +00:00
registers	amd/registers: fix fields conflict detection	2021-07-30 08:50:38 +00:00
vulkan	radv: fix missing cache flushes when clearing HTILE levels on GFX10+	2021-08-03 12:59:57 +00:00
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meson.build	…