mesa/src/panfrost/midgard
Alyssa Rosenzweig 829f769e60 pan/mdg: Fix 16-bit alignment with spiller
The loop over sources has to happen for every instruction, regardless of whether
we also need to register allocate the destination. The other source loops handle
this properly, but this one was missed.

Fixes spilling failure in shaders/android/angle/aztec_ruins/16.shader_test when
the input NIR is shuffled a bit (from reordering passes).

Fixes: 129d390bd8 ("pan/mdg: Fix bound setting in RA for sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19093>
2022-10-17 19:11:10 +00:00
..
compiler.h
disassemble.c pan/mdg: Remove disassembler stats 2022-08-17 17:25:56 +00:00
disassemble.h pan/mdg: Remove disassembler stats 2022-08-17 17:25:56 +00:00
helpers.h
meson.build
midgard.h
midgard_address.c
midgard_compile.c panfrost: Remove load_kernel_input path 2022-10-05 16:09:21 +00:00
midgard_compile.h
midgard_derivatives.c
midgard_emit.c pan/mdg: Reexpress umul_high packing 2022-08-24 19:54:23 +00:00
midgard_errata_lod.c nir: adjust nir_src_copy signature to take a nir_instr * 2022-08-30 18:21:44 +00:00
midgard_helper_invocations.c
midgard_liveness.c
midgard_nir.h
midgard_nir_algebraic.py
midgard_nir_lower_helper_writes.c
midgard_nir_lower_image_bitsize.c
midgard_ops.c
midgard_ops.h
midgard_opt_copy_prop.c
midgard_opt_dce.c
midgard_opt_perspective.c
midgard_print.c pan/mdg: Print 3 sources for CSEL 2022-08-31 14:07:53 +00:00
midgard_print_constant.c
midgard_quirks.h
midgard_ra.c pan/mdg: Fix 16-bit alignment with spiller 2022-10-17 19:11:10 +00:00
midgard_ra_pipeline.c
midgard_schedule.c pan/mdg: Always write return address to r1.w 2022-08-31 14:07:53 +00:00
mir.c
mir_promote_uniforms.c
mir_squeeze.c
nir_fuse_io_16.c