Timur Kristóf dd90273aaa aco: Optimize MUBUF 0 offset when idxen is also being used. ... Now that we added an index src to the NIR intrinsic, it can happen that these generate MUBUF instructions which have both an index and an offset. Extend this ACO optimization to the case when idxen is used. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17551>		2022-10-20 20:00:50 +00:00
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addrlib	amd/addrlib: fix 3D texture allocation failures on gfx11	2022-08-03 00:57:16 +00:00
ci	radeonsi,radv/ci: Increase coverage	2022-10-20 08:03:05 +00:00
common	nir, ac, aco: Add index src to load_buffer_amd/store_buffer_amd.	2022-10-20 20:00:50 +00:00
compiler	aco: Optimize MUBUF 0 offset when idxen is also being used.	2022-10-20 20:00:50 +00:00
drm-shim	…
llvm	nir, ac, aco: Add index src to load_buffer_amd/store_buffer_amd.	2022-10-20 20:00:50 +00:00
registers	winsys/amdgpu: fix (enable) preemption for chained IBs	2022-10-18 22:42:28 +00:00
vulkan	radv: add lowering for nir_intrinsic_load_ring_attr_{offset}_amd	2022-10-20 15:59:44 +00:00
.clang-format	…
meson.build	…