mirror of https://gitlab.freedesktop.org/mesa/mesa
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/*
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* Copyright (C) 2019 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors (Collabora):
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* Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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*/
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#include "compiler.h"
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/* When we're 'squeezing down' the values in the IR, we maintain a hash
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* as such */
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static unsigned
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find_or_allocate_temp(compiler_context *ctx, struct hash_table_u64 *map,
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unsigned hash)
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{
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if (hash >= SSA_FIXED_MINIMUM)
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return hash;
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unsigned temp = (uintptr_t)_mesa_hash_table_u64_search(map, hash + 1);
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if (temp)
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return temp - 1;
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/* If no temp is find, allocate one */
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temp = ctx->temp_count++;
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ctx->max_hash = MAX2(ctx->max_hash, hash);
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_mesa_hash_table_u64_insert(map, hash + 1, (void *)((uintptr_t)temp + 1));
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return temp;
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}
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/* Reassigns numbering to get rid of gaps in the indices and to prioritize
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* smaller register classes */
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void
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mir_squeeze_index(compiler_context *ctx)
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{
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struct hash_table_u64 *map = _mesa_hash_table_u64_create(NULL);
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/* Reset */
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ctx->temp_count = 0;
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/* We need to prioritize texture registers on older GPUs so we don't
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* fail RA trying to assign to work registers r0/r1 when a work
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* register is already there */
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mir_foreach_instr_global(ctx, ins) {
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if (ins->type == TAG_TEXTURE_4)
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ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
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}
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mir_foreach_instr_global(ctx, ins) {
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if (ins->type != TAG_TEXTURE_4)
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ins->dest = find_or_allocate_temp(ctx, map, ins->dest);
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for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i)
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ins->src[i] = find_or_allocate_temp(ctx, map, ins->src[i]);
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}
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ctx->blend_input = find_or_allocate_temp(ctx, map, ctx->blend_input);
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ctx->blend_src1 = find_or_allocate_temp(ctx, map, ctx->blend_src1);
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_mesa_hash_table_u64_destroy(map);
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}
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