mirror of https://gitlab.freedesktop.org/mesa/mesa
502 lines
14 KiB
C
502 lines
14 KiB
C
/*
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* Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Copyright (C) 2019-2020 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler.h"
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#include "midgard_ops.h"
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void
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mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old,
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unsigned new)
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{
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mir_foreach_src(ins, i) {
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if (ins->src[i] == old)
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ins->src[i] = new;
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}
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}
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void
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mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old,
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unsigned new)
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{
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if (ins->dest == old)
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ins->dest = new;
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}
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static void
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mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old,
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unsigned new, unsigned *swizzle)
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{
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for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
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if (ins->src[i] != old)
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continue;
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ins->src[i] = new;
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mir_compose_swizzle(ins->swizzle[i], swizzle, ins->swizzle[i]);
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}
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}
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void
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mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
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{
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mir_foreach_instr_global(ctx, ins) {
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mir_rewrite_index_src_single(ins, old, new);
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}
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}
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void
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mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new,
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unsigned *swizzle)
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{
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mir_foreach_instr_global(ctx, ins) {
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mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
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}
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}
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void
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mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
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{
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mir_foreach_instr_global(ctx, ins) {
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mir_rewrite_index_dst_single(ins, old, new);
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}
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/* Implicitly written before the shader */
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if (ctx->blend_input == old)
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ctx->blend_input = new;
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if (ctx->blend_src1 == old)
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ctx->blend_src1 = new;
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}
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void
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mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
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{
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mir_rewrite_index_src(ctx, old, new);
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mir_rewrite_index_dst(ctx, old, new);
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}
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unsigned
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mir_use_count(compiler_context *ctx, unsigned value)
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{
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unsigned used_count = 0;
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mir_foreach_instr_global(ctx, ins) {
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if (mir_has_arg(ins, value))
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++used_count;
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}
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if (ctx->blend_input == value)
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++used_count;
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if (ctx->blend_src1 == value)
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++used_count;
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return used_count;
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}
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/* Checks if a value is used only once (or totally dead), which is an important
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* heuristic to figure out if certain optimizations are Worth It (TM) */
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bool
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mir_single_use(compiler_context *ctx, unsigned value)
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{
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/* We can replicate constants in places so who cares */
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if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
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return true;
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return mir_use_count(ctx, value) <= 1;
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}
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bool
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mir_nontrivial_mod(midgard_instruction *ins, unsigned i, bool check_swizzle)
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{
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bool is_int = midgard_is_integer_op(ins->op);
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if (is_int) {
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if (ins->src_shift[i])
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return true;
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} else {
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if (ins->src_neg[i])
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return true;
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if (ins->src_abs[i])
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return true;
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}
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if (ins->dest_type != ins->src_types[i])
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return true;
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if (check_swizzle) {
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for (unsigned c = 0; c < 16; ++c) {
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if (!(ins->mask & (1 << c)))
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continue;
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if (ins->swizzle[i][c] != c)
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return true;
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}
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}
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return false;
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}
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bool
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mir_nontrivial_outmod(midgard_instruction *ins)
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{
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bool is_int = midgard_is_integer_op(ins->op);
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unsigned mod = ins->outmod;
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if (ins->dest_type != ins->src_types[1])
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return true;
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if (is_int)
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return mod != midgard_outmod_keeplo;
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else
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return mod != midgard_outmod_none;
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}
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/* 128 / sz = exp2(log2(128 / sz))
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* = exp2(log2(128) - log2(sz))
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* = exp2(7 - log2(sz))
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* = 1 << (7 - log2(sz))
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*/
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static unsigned
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mir_components_for_bits(unsigned bits)
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{
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return 1 << (7 - util_logbase2(bits));
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}
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unsigned
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mir_components_for_type(nir_alu_type T)
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{
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unsigned sz = nir_alu_type_get_type_size(T);
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return mir_components_for_bits(sz);
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}
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uint16_t
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mir_from_bytemask(uint16_t bytemask, unsigned bits)
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{
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unsigned value = 0;
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unsigned count = bits / 8;
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for (unsigned c = 0, d = 0; c < 16; c += count, ++d) {
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bool a = (bytemask & (1 << c)) != 0;
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for (unsigned q = c; q < count; ++q)
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assert(((bytemask & (1 << q)) != 0) == a);
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value |= (a << d);
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}
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return value;
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}
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/* Rounds up a bytemask to fill a given component count. Iterate each
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* component, and check if any bytes in the component are masked on */
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uint16_t
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mir_round_bytemask_up(uint16_t mask, unsigned bits)
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{
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unsigned bytes = bits / 8;
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unsigned maxmask = mask_of(bytes);
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unsigned channels = mir_components_for_bits(bits);
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for (unsigned c = 0; c < channels; ++c) {
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unsigned submask = maxmask << (c * bytes);
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if (mask & submask)
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mask |= submask;
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}
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return mask;
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}
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/* Grabs the per-byte mask of an instruction (as opposed to per-component) */
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uint16_t
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mir_bytemask(midgard_instruction *ins)
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{
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unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
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return pan_to_bytemask(type_size, ins->mask);
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}
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void
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mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask)
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{
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unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
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ins->mask = mir_from_bytemask(bytemask, type_size);
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}
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/*
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* Checks if we should use an upper destination override, rather than the lower
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* one in the IR. If yes, returns the bytes to shift by. If no, returns zero
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* for a lower override and negative for no override.
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*/
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signed
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mir_upper_override(midgard_instruction *ins, unsigned inst_size)
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{
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unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);
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/* If the sizes are the same, there's nothing to override */
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if (type_size == inst_size)
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return -1;
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/* There are 16 bytes per vector, so there are (16/bytes)
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* components per vector. So the magic half is half of
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* (16/bytes), which simplifies to 8/bytes = 8 / (bits / 8) = 64 / bits
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* */
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unsigned threshold = mir_components_for_bits(type_size) >> 1;
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/* How many components did we shift over? */
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unsigned zeroes = __builtin_ctz(ins->mask);
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/* Did we hit the threshold? */
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return (zeroes >= threshold) ? threshold : 0;
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}
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/* Creates a mask of the components of a node read by an instruction, by
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* analyzing the swizzle with respect to the instruction's mask. E.g.:
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*
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* fadd r0.xz, r1.yyyy, r2.zwyx
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*
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* will return a mask of Z/Y for r2
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*/
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static uint16_t
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mir_bytemask_of_read_components_single(unsigned *swizzle, unsigned inmask,
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unsigned bits)
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{
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unsigned cmask = 0;
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for (unsigned c = 0; c < MIR_VEC_COMPONENTS; ++c) {
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if (!(inmask & (1 << c)))
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continue;
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cmask |= (1 << swizzle[c]);
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}
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return pan_to_bytemask(bits, cmask);
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}
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uint16_t
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mir_bytemask_of_read_components_index(midgard_instruction *ins, unsigned i)
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{
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/* Conditional branches read one 32-bit component = 4 bytes (TODO: multi
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* branch??) */
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if (ins->compact_branch && ins->branch.conditional && (i == 0))
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return 0xF;
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/* ALU ops act componentwise so we need to pay attention to
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* their mask. Texture/ldst does not so we don't clamp source
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* readmasks based on the writemask */
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unsigned qmask = ~0;
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/* Handle dot products and things */
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if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
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unsigned props = alu_opcode_props[ins->op].props;
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unsigned channel_override = GET_CHANNEL_COUNT(props);
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if (channel_override)
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qmask = mask_of(channel_override);
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else
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qmask = ins->mask;
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}
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return mir_bytemask_of_read_components_single(
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ins->swizzle[i], qmask, nir_alu_type_get_type_size(ins->src_types[i]));
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}
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uint16_t
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mir_bytemask_of_read_components(midgard_instruction *ins, unsigned node)
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{
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uint16_t mask = 0;
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if (node == ~0)
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return 0;
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mir_foreach_src(ins, i) {
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if (ins->src[i] != node)
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continue;
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mask |= mir_bytemask_of_read_components_index(ins, i);
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}
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return mask;
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}
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/* Register allocation occurs after instruction scheduling, which is fine until
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* we start needing to spill registers and therefore insert instructions into
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* an already-scheduled program. We don't have to be terribly efficient about
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* this, since spilling is already slow. So just semantically we need to insert
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* the instruction into a new bundle before/after the bundle of the instruction
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* in question */
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static midgard_bundle
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mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
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{
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midgard_instruction *u = mir_upload_ins(ctx, ins);
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midgard_bundle bundle = {
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.tag = ins.type,
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.instruction_count = 1,
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.instructions = {u},
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};
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if (bundle.tag == TAG_ALU_4) {
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assert(OP_IS_MOVE(u->op));
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u->unit = UNIT_VMUL;
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size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) +
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sizeof(midgard_vector_alu);
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bundle.padding = ~(bytes_emitted - 1) & 0xF;
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bundle.control = ins.type | u->unit;
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}
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return bundle;
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}
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static unsigned
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mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
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{
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midgard_bundle *bundles = (midgard_bundle *)block->bundles.data;
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size_t count = (block->bundles.size / sizeof(midgard_bundle));
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for (unsigned i = 0; i < count; ++i) {
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for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
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if (bundles[i].instructions[j] == tag)
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return i;
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}
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}
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mir_print_instruction(tag);
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unreachable("Instruction not scheduled in block");
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}
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midgard_instruction *
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mir_insert_instruction_before_scheduled(compiler_context *ctx,
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midgard_block *block,
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midgard_instruction *tag,
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midgard_instruction ins)
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{
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unsigned before = mir_bundle_idx_for_ins(tag, block);
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size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
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UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
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midgard_bundle *bundles = (midgard_bundle *)block->bundles.data;
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memmove(bundles + before + 1, bundles + before,
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(count - before) * sizeof(midgard_bundle));
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midgard_bundle *before_bundle = bundles + before + 1;
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midgard_bundle new = mir_bundle_for_op(ctx, ins);
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memcpy(bundles + before, &new, sizeof(new));
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list_addtail(&new.instructions[0]->link,
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&before_bundle->instructions[0]->link);
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block->quadword_count += midgard_tag_props[new.tag].size;
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return new.instructions[0];
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}
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midgard_instruction *
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mir_insert_instruction_after_scheduled(compiler_context *ctx,
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midgard_block *block,
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midgard_instruction *tag,
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midgard_instruction ins)
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{
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/* We need to grow the bundles array to add our new bundle */
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size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
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UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
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/* Find the bundle that we want to insert after */
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unsigned after = mir_bundle_idx_for_ins(tag, block);
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/* All the bundles after that one, we move ahead by one */
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midgard_bundle *bundles = (midgard_bundle *)block->bundles.data;
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memmove(bundles + after + 2, bundles + after + 1,
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(count - after - 1) * sizeof(midgard_bundle));
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midgard_bundle *after_bundle = bundles + after;
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midgard_bundle new = mir_bundle_for_op(ctx, ins);
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memcpy(bundles + after + 1, &new, sizeof(new));
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list_add(
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&new.instructions[0]->link,
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&after_bundle->instructions[after_bundle->instruction_count - 1]->link);
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block->quadword_count += midgard_tag_props[new.tag].size;
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return new.instructions[0];
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}
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/* Flip the first-two arguments of a (binary) op. Currently ALU
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* only, no known uses for ldst/tex */
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void
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mir_flip(midgard_instruction *ins)
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{
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unsigned temp = ins->src[0];
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ins->src[0] = ins->src[1];
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ins->src[1] = temp;
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assert(ins->type == TAG_ALU_4);
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temp = ins->src_types[0];
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ins->src_types[0] = ins->src_types[1];
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ins->src_types[1] = temp;
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temp = ins->src_abs[0];
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ins->src_abs[0] = ins->src_abs[1];
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ins->src_abs[1] = temp;
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temp = ins->src_neg[0];
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ins->src_neg[0] = ins->src_neg[1];
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ins->src_neg[1] = temp;
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temp = ins->src_invert[0];
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ins->src_invert[0] = ins->src_invert[1];
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ins->src_invert[1] = temp;
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unsigned temp_swizzle[16];
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memcpy(temp_swizzle, ins->swizzle[0], sizeof(ins->swizzle[0]));
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memcpy(ins->swizzle[0], ins->swizzle[1], sizeof(ins->swizzle[0]));
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memcpy(ins->swizzle[1], temp_swizzle, sizeof(ins->swizzle[0]));
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}
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/* Before squashing, calculate ctx->temp_count just by observing the MIR */
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void
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mir_compute_temp_count(compiler_context *ctx)
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{
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unsigned max_index = 0;
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mir_foreach_instr_global(ctx, ins) {
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if (ins->dest < SSA_FIXED_MINIMUM)
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max_index = MAX2(max_index, ins->dest + 1);
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}
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if (ctx->blend_input != ~0)
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max_index = MAX2(max_index, ctx->blend_input + 1);
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if (ctx->blend_src1 != ~0)
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max_index = MAX2(max_index, ctx->blend_src1 + 1);
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ctx->temp_count = max_index;
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}
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