mirror of https://gitlab.freedesktop.org/mesa/mesa
107 lines
3.8 KiB
C
107 lines
3.8 KiB
C
/*
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* Copyright (C) 2019 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MDG_QUIRKS_H
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#define __MDG_QUIRKS_H
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/* Model-specific quirks requiring compiler workarounds/etc. Quirks
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* may be errata requiring a workaround, or features. We're trying to be
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* quirk-positive here; quirky is the best! */
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/* Typed loads are broken on this Midgard GPU due to issue #10607 and #10632 and
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* should use software unpacks instead.
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*/
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#define MIDGARD_BROKEN_BLEND_LOADS (1 << 0)
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/* Whether output texture registers (normally r28/r29) overlap with work
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* registers r0/r1 and input texture registers (also normally r28/r29) overlap
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* with load/store registers r26/r27. This constrains register allocation
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* considerably but is a space-saving measure on small Midgards. It's worth
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* noting if you try to access r28/r29, it may still work, but you'll mess up
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* the interference. Corresponds to BASE_HW_FEATURE_INTERPIPE_REG_ALIASING in
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* kbase. */
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#define MIDGARD_INTERPIPE_REG_ALIASING (1 << 1)
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/* Whether we should use old-style blend opcodes */
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#define MIDGARD_OLD_BLEND (1 << 2)
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/* Errata causing the LOD clamps and bias in the sampler descriptor to be
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* ignored. This errata affects the command stream but uses a compiler
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* workaround (applying the clamps/bias manually in the shader. Corresponds in
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* BASE_HW_ISSUE_10471 in kbase, described as "TEXGRD doesn't honor Sampler
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* Descriptor LOD clamps nor bias". (I'm assuming TEXGRD is what we call
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* textureLod) */
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#define MIDGARD_BROKEN_LOD (1 << 3)
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/* Don't use upper ALU tags for writeout (if you do, you'll get a
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* INSTR_INVALID_ENC). It's not clear to me what these tags are for. */
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#define MIDGARD_NO_UPPER_ALU (1 << 4)
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/* Whether (texture) out-of-order execution support is missing on early
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* Midgards. For these just set the OoO bits to 0. */
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#define MIDGARD_NO_OOO (1 << 5)
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/* Disable auto32 type (apparently broken on T60x). */
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#define MIDGARD_NO_AUTO32 (1 << 6)
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static inline unsigned
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midgard_get_quirks(unsigned gpu_id)
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{
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switch (gpu_id) {
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case 0x600:
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return MIDGARD_OLD_BLEND | MIDGARD_BROKEN_BLEND_LOADS |
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MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO |
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MIDGARD_NO_AUTO32;
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case 0x620:
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return MIDGARD_OLD_BLEND | MIDGARD_BROKEN_BLEND_LOADS |
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MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO;
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case 0x720:
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return MIDGARD_INTERPIPE_REG_ALIASING | MIDGARD_OLD_BLEND |
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MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO;
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case 0x820:
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case 0x830:
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return MIDGARD_INTERPIPE_REG_ALIASING;
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case 0x750:
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return MIDGARD_NO_UPPER_ALU;
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case 0x860:
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case 0x880:
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return 0;
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default:
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unreachable("Invalid Midgard GPU ID");
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}
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}
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#endif
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