mirror of https://gitlab.freedesktop.org/mesa/mesa
264 lines
8.8 KiB
C
264 lines
8.8 KiB
C
/*
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* Copyright (C) 2021 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef __PAN_SHADER_H__
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#define __PAN_SHADER_H__
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#include "compiler/nir/nir.h"
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#include "panfrost/util/pan_ir.h"
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#include "panfrost/util/pan_lower_framebuffer.h"
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#include "genxml/gen_macros.h"
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void bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id);
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void midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id);
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static inline void
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pan_shader_preprocess(nir_shader *nir, unsigned gpu_id)
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{
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if (pan_arch(gpu_id) >= 6)
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bifrost_preprocess_nir(nir, gpu_id);
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else
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midgard_preprocess_nir(nir, gpu_id);
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}
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uint8_t pan_raw_format_mask_midgard(enum pipe_format *formats);
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#ifdef PAN_ARCH
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const nir_shader_compiler_options *GENX(pan_shader_get_compiler_options)(void);
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void GENX(pan_shader_compile)(nir_shader *nir,
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struct panfrost_compile_inputs *inputs,
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struct util_dynarray *binary,
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struct pan_shader_info *info);
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#if PAN_ARCH >= 6 && PAN_ARCH <= 7
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enum mali_register_file_format
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GENX(pan_fixup_blend_type)(nir_alu_type T_size, enum pipe_format format);
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#endif
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#if PAN_ARCH >= 9
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static inline enum mali_shader_stage
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pan_shader_stage(const struct pan_shader_info *info)
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{
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switch (info->stage) {
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case MESA_SHADER_VERTEX:
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return MALI_SHADER_STAGE_VERTEX;
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case MESA_SHADER_FRAGMENT:
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return MALI_SHADER_STAGE_FRAGMENT;
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default:
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return MALI_SHADER_STAGE_COMPUTE;
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}
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}
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#endif
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#if PAN_ARCH >= 7
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static inline enum mali_shader_register_allocation
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pan_register_allocation(unsigned work_reg_count)
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{
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return (work_reg_count <= 32)
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? MALI_SHADER_REGISTER_ALLOCATION_32_PER_THREAD
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: MALI_SHADER_REGISTER_ALLOCATION_64_PER_THREAD;
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}
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#endif
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static inline enum mali_depth_source
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pan_depth_source(const struct pan_shader_info *info)
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{
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return info->fs.writes_depth ? MALI_DEPTH_SOURCE_SHADER
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: MALI_DEPTH_SOURCE_FIXED_FUNCTION;
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}
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#if PAN_ARCH <= 7
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#if PAN_ARCH <= 5
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static inline void
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pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
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struct MALI_RENDERER_STATE *rsd)
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{
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assert((info->push.count & 3) == 0);
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rsd->properties.uniform_count = info->push.count / 4;
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rsd->properties.shader_has_side_effects = info->writes_global;
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rsd->properties.fp_mode = MALI_FP_MODE_GL_INF_NAN_ALLOWED;
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/* For fragment shaders, work register count, early-z, reads at draw-time */
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if (info->stage != MESA_SHADER_FRAGMENT) {
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rsd->properties.work_register_count = info->work_reg_count;
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} else {
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rsd->properties.shader_reads_tilebuffer = info->fs.outputs_read;
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/* However, forcing early-z in the shader overrides draw-time */
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rsd->properties.force_early_z = info->fs.early_fragment_tests;
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}
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}
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#else
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#define pan_preloads(reg) (preload & BITFIELD64_BIT(reg))
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static void
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pan_make_preload(gl_shader_stage stage, uint64_t preload,
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struct MALI_PRELOAD *out)
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{
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switch (stage) {
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case MESA_SHADER_VERTEX:
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out->vertex.position_result_address_lo = pan_preloads(58);
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out->vertex.position_result_address_hi = pan_preloads(59);
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out->vertex.vertex_id = pan_preloads(61);
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out->vertex.instance_id = pan_preloads(62);
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break;
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case MESA_SHADER_FRAGMENT:
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out->fragment.primitive_id = pan_preloads(57);
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out->fragment.primitive_flags = pan_preloads(58);
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out->fragment.fragment_position = pan_preloads(59);
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out->fragment.sample_mask_id = pan_preloads(61);
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out->fragment.coverage = true;
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break;
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default:
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out->compute.local_invocation_xy = pan_preloads(55);
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out->compute.local_invocation_z = pan_preloads(56);
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out->compute.work_group_x = pan_preloads(57);
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out->compute.work_group_y = pan_preloads(58);
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out->compute.work_group_z = pan_preloads(59);
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out->compute.global_invocation_x = pan_preloads(60);
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out->compute.global_invocation_y = pan_preloads(61);
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out->compute.global_invocation_z = pan_preloads(62);
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break;
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}
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}
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#if PAN_ARCH == 7
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static inline void
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pan_pack_message_preload(struct MALI_MESSAGE_PRELOAD *cfg,
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const struct bifrost_message_preload *msg)
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{
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enum mali_message_preload_register_format regfmt =
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msg->fp16 ? MALI_MESSAGE_PRELOAD_REGISTER_FORMAT_F16
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: MALI_MESSAGE_PRELOAD_REGISTER_FORMAT_F32;
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if (msg->enabled && msg->texture) {
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cfg->type = MALI_MESSAGE_TYPE_VAR_TEX;
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cfg->var_tex.varying_index = msg->varying_index;
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cfg->var_tex.texture_index = msg->texture_index;
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cfg->var_tex.register_format = regfmt;
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cfg->var_tex.skip = msg->skip;
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cfg->var_tex.zero_lod = msg->zero_lod;
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} else if (msg->enabled) {
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cfg->type = MALI_MESSAGE_TYPE_LD_VAR;
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cfg->ld_var.varying_index = msg->varying_index;
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cfg->ld_var.register_format = regfmt;
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cfg->ld_var.num_components = msg->num_components;
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} else {
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cfg->type = MALI_MESSAGE_TYPE_DISABLED;
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}
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}
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#endif
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static inline void
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pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
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struct MALI_RENDERER_STATE *rsd)
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{
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unsigned fau_count = DIV_ROUND_UP(info->push.count, 2);
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rsd->preload.uniform_count = fau_count;
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#if PAN_ARCH >= 7
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rsd->properties.shader_register_allocation =
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pan_register_allocation(info->work_reg_count);
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#endif
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pan_make_preload(info->stage, info->preload, &rsd->preload);
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if (info->stage == MESA_SHADER_FRAGMENT) {
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rsd->properties.shader_modifies_coverage =
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info->fs.writes_coverage || info->fs.can_discard;
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rsd->properties.allow_forward_pixel_to_be_killed = !info->writes_global;
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#if PAN_ARCH >= 7
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rsd->properties.shader_wait_dependency_6 = info->bifrost.wait_6;
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rsd->properties.shader_wait_dependency_7 = info->bifrost.wait_7;
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pan_pack_message_preload(&rsd->message_preload_1,
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&info->bifrost.messages[0]);
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pan_pack_message_preload(&rsd->message_preload_2,
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&info->bifrost.messages[1]);
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#endif
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} else if (info->stage == MESA_SHADER_VERTEX && info->vs.secondary_enable) {
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rsd->secondary_preload.uniform_count = fau_count;
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pan_make_preload(info->stage, info->vs.secondary_preload,
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&rsd->secondary_preload);
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rsd->secondary_shader = rsd->shader.shader + info->vs.secondary_offset;
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#if PAN_ARCH >= 7
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rsd->properties.secondary_shader_register_allocation =
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pan_register_allocation(info->vs.secondary_work_reg_count);
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#endif
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}
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}
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#endif
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static inline void
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pan_shader_prepare_rsd(const struct pan_shader_info *shader_info,
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mali_ptr shader_ptr, struct MALI_RENDERER_STATE *rsd)
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{
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#if PAN_ARCH <= 5
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shader_ptr |= shader_info->midgard.first_tag;
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#endif
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rsd->shader.shader = shader_ptr;
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rsd->shader.attribute_count = shader_info->attribute_count;
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rsd->shader.varying_count =
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shader_info->varyings.input_count + shader_info->varyings.output_count;
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rsd->shader.texture_count = shader_info->texture_count;
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rsd->shader.sampler_count = shader_info->sampler_count;
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rsd->properties.shader_contains_barrier = shader_info->contains_barrier;
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rsd->properties.uniform_buffer_count = shader_info->ubo_count;
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if (shader_info->stage == MESA_SHADER_FRAGMENT) {
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rsd->properties.stencil_from_shader = shader_info->fs.writes_stencil;
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rsd->properties.depth_source = pan_depth_source(shader_info);
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/* This also needs to be set if the API forces per-sample
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* shading, but that'll just got ORed in */
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rsd->multisample_misc.evaluate_per_sample =
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shader_info->fs.sample_shading;
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}
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#if PAN_ARCH >= 6
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pan_shader_prepare_bifrost_rsd(shader_info, rsd);
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#else
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pan_shader_prepare_midgard_rsd(shader_info, rsd);
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#endif
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}
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#endif /* PAN_ARCH */
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#endif
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#endif
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