mirror of https://gitlab.freedesktop.org/mesa/mesa
245 lines
7.9 KiB
C
245 lines
7.9 KiB
C
/*
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* Copyright (C) 2019 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors (Collabora):
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* Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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*/
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#ifndef __PAN_ENCODER_H
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#define __PAN_ENCODER_H
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#include "util/macros.h"
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#include <stdbool.h>
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#include "genxml/gen_macros.h"
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#include "util/format/u_format.h"
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#include "pan_pool.h"
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/* Tiler structure size computation */
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unsigned panfrost_tiler_header_size(unsigned width, unsigned height,
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unsigned mask, bool hierarchy);
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unsigned panfrost_tiler_full_size(unsigned width, unsigned height,
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unsigned mask, bool hierarchy);
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unsigned panfrost_choose_hierarchy_mask(unsigned width, unsigned height,
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unsigned vertex_count, bool hierarchy);
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#if defined(PAN_ARCH) && PAN_ARCH <= 5
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static inline unsigned
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panfrost_tiler_get_polygon_list_size(unsigned fb_width, unsigned fb_height,
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unsigned vertex_count, bool hierarchy)
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{
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if (!vertex_count)
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return MALI_MIDGARD_TILER_MINIMUM_HEADER_SIZE + 4;
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unsigned hierarchy_mask = panfrost_choose_hierarchy_mask(
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fb_width, fb_height, vertex_count, hierarchy);
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return panfrost_tiler_full_size(fb_width, fb_height, hierarchy_mask,
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hierarchy) +
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panfrost_tiler_header_size(fb_width, fb_height, hierarchy_mask,
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hierarchy);
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}
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#endif
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/* Stack sizes */
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unsigned panfrost_get_stack_shift(unsigned stack_size);
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unsigned panfrost_get_total_stack_size(unsigned thread_size,
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unsigned threads_per_core,
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unsigned core_id_range);
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/* Attributes / instancing */
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unsigned panfrost_padded_vertex_count(unsigned vertex_count);
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unsigned panfrost_compute_magic_divisor(unsigned hw_divisor, unsigned *o_shift,
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unsigned *extra_flags);
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#ifdef PAN_ARCH
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/* Records for gl_VertexID and gl_InstanceID use special encodings on Midgard */
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#if PAN_ARCH <= 5
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static inline void
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panfrost_vertex_id(unsigned padded_count,
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struct mali_attribute_buffer_packed *attr, bool instanced)
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{
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pan_pack(attr, ATTRIBUTE_VERTEX_ID, cfg) {
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if (instanced) {
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cfg.divisor_r = __builtin_ctz(padded_count);
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cfg.divisor_p = padded_count >> (cfg.divisor_r + 1);
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} else {
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/* Large values so the modulo is a no-op */
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cfg.divisor_r = 0x1F;
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cfg.divisor_p = 0x4;
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}
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}
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}
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static inline void
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panfrost_instance_id(unsigned padded_count,
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struct mali_attribute_buffer_packed *attr, bool instanced)
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{
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pan_pack(attr, ATTRIBUTE_INSTANCE_ID, cfg) {
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if (!instanced || padded_count <= 1) {
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/* Divide by large number to force to 0 */
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cfg.divisor_p = ((1u << 31) - 1);
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cfg.divisor_r = 0x1F;
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cfg.divisor_e = 0x1;
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} else if (util_is_power_of_two_or_zero(padded_count)) {
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/* Can't underflow since padded_count >= 2 */
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cfg.divisor_r = __builtin_ctz(padded_count) - 1;
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} else {
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cfg.divisor_p = panfrost_compute_magic_divisor(
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padded_count, &cfg.divisor_r, &cfg.divisor_e);
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}
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}
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}
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#endif /* PAN_ARCH <= 5 */
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/* Sampler comparison functions are flipped in OpenGL from the hardware, so we
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* need to be able to flip accordingly */
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static inline enum mali_func
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panfrost_flip_compare_func(enum mali_func f)
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{
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switch (f) {
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case MALI_FUNC_LESS:
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return MALI_FUNC_GREATER;
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case MALI_FUNC_GREATER:
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return MALI_FUNC_LESS;
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case MALI_FUNC_LEQUAL:
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return MALI_FUNC_GEQUAL;
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case MALI_FUNC_GEQUAL:
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return MALI_FUNC_LEQUAL;
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default:
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return f;
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}
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}
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#if PAN_ARCH <= 7
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/* Compute shaders are invoked with a gl_NumWorkGroups X/Y/Z triplet. Vertex
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* shaders are invoked as (1, vertex_count, instance_count). Compute shaders
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* also have a gl_WorkGroupSize X/Y/Z triplet. These 6 values are packed
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* together in a dynamic bitfield, packed by this routine. */
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static inline void
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panfrost_pack_work_groups_compute(struct mali_invocation_packed *out,
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unsigned num_x, unsigned num_y,
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unsigned num_z, unsigned size_x,
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unsigned size_y, unsigned size_z,
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bool quirk_graphics, bool indirect_dispatch)
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{
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/* The values needing packing, in order, and the corresponding shifts.
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* Indicies into shift are off-by-one to make the logic easier */
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unsigned values[6] = {size_x, size_y, size_z, num_x, num_y, num_z};
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unsigned shifts[7] = {0};
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uint32_t packed = 0;
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for (unsigned i = 0; i < 6; ++i) {
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/* Must be positive, otherwise we underflow */
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assert(values[i] >= 1);
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/* OR it in, shifting as required */
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packed |= ((values[i] - 1) << shifts[i]);
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/* How many bits did we use? */
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unsigned bit_count = util_logbase2_ceil(values[i]);
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/* Set the next shift accordingly */
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shifts[i + 1] = shifts[i] + bit_count;
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}
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pan_pack(out, INVOCATION, cfg) {
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cfg.invocations = packed;
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cfg.size_y_shift = shifts[1];
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cfg.size_z_shift = shifts[2];
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cfg.workgroups_x_shift = shifts[3];
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if (!indirect_dispatch) {
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/* Leave zero for the dispatch shader */
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cfg.workgroups_y_shift = shifts[4];
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cfg.workgroups_z_shift = shifts[5];
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}
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/* Quirk: for non-instanced graphics, the blob sets
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* workgroups_z_shift = 32. This doesn't appear to matter to
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* the hardware, but it's good to be bit-identical. */
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if (quirk_graphics && (num_z <= 1))
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cfg.workgroups_z_shift = 32;
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/* For graphics, set to the minimum efficient value. For
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* compute, must equal the workgroup X shift for barriers to
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* function correctly */
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cfg.thread_group_split =
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quirk_graphics ? MALI_SPLIT_MIN_EFFICIENT : cfg.workgroups_x_shift;
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}
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}
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#endif
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#if PAN_ARCH >= 5
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/* Format conversion */
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static inline enum mali_z_internal_format
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panfrost_get_z_internal_format(enum pipe_format fmt)
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{
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switch (fmt) {
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case PIPE_FORMAT_Z16_UNORM:
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case PIPE_FORMAT_Z16_UNORM_S8_UINT:
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return MALI_Z_INTERNAL_FORMAT_D16;
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case PIPE_FORMAT_Z24_UNORM_S8_UINT:
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case PIPE_FORMAT_Z24X8_UNORM:
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return MALI_Z_INTERNAL_FORMAT_D24;
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case PIPE_FORMAT_Z32_FLOAT:
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case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
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return MALI_Z_INTERNAL_FORMAT_D32;
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default:
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unreachable("Unsupported depth/stencil format.");
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}
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}
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#endif
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#endif /* PAN_ARCH */
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#if PAN_ARCH >= 9
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static inline void
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panfrost_make_resource_table(struct panfrost_ptr base, unsigned index,
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mali_ptr address, unsigned resource_count)
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{
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if (resource_count == 0)
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return;
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pan_pack(base.cpu + index * pan_size(RESOURCE), RESOURCE, cfg) {
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cfg.address = address;
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cfg.size = resource_count * pan_size(BUFFER);
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}
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}
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#endif
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#endif
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